AT91SAM9263B-CU Atmel, AT91SAM9263B-CU Datasheet - Page 921

• Manufacturer Part Number: AT91SAM9263B-CU
• Description: IC ARM9 MCU 200 MHZ 324-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9263B-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 240MHz
• Connectivity: CAN, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: 2-Wire, EBI, I2S, MCI, SPI, USART
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9263-EK
• Minimum Operating Temperature: - 40 C
• Package: 324TFBGA
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 200 MHz
• Operating Supply Voltage: 1.8|2.5|3.3 V
• Controller Family/series: AT91SAM9xxx
• No. Of I/o's: 160
• Ram Memory Size: 96KB
• Cpu Speed: 240MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• For Use With: AT91SAM9263-EK - KIT EVAL FOR AT91SAM9263AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q3735625

44.8
6249H–ATARM–27-Jul-09
Double-buffer Technique
The double-buffer technique is used to avoid flickering while the frame being displayed is
updated. Instead of using a single buffer, there are two different buffers, the backbuffer (back-
ground buffer) and the primary buffer (the buffer being displayed).
• Configure the DMA Controller. The user should configure the base address of the display
• Finally, enable the LCD Controller Core by writing a “1” in the LCD_PWR field of the
buffer memory, the size of the AHB transaction and the size of the display image in memory.
When the DMA is configured the user should enable the DMA. To do so the user should
configure the following registers:
PWRCON register and do any other action that may be required to turn the LCD module on.
– LCDCON2 register: Program its fields following their descriptions in the LCD
– LCDTIM1 and LCDTIM2 registers: Program their fields according to the datasheet of
– LCDFRMCFG register: program the dimensions of the LCD module used.
– LCDFIFO register: To program it, use the formula in section
– DP1_2 to DP6_7 registers: they are only used for STN displays. They contain the
– PWRCON Register: this register controls the power-up sequence of the LCD, so
– CONTRAST_CTR and CONTRAST_VAL: use this registers to adjust the contrast of
– DMABADDR1 and DMABADDR2 registers: In single scan mode only DMABADDR1
– DMAFRMCFG register: Program the FRMSIZE field. Note that in dual scan mode
– DMACON register: Once both the LCD Controller Core and the DMA Controller have
– DMA2DCFG register: Required only in 2D memory addressing mode (see
Controller User Interface section below and considering the type of LCD module
used and the desired working mode. Consider that not all combinations are possible.
the LCD module used and with the help of the Timegen section in page 10. Note that
some fields are not applicable to STN modules and must be programmed with 0
values. Note also that there is a limitation on the minimum value of VHDLY, HPW,
HBP that depends on the configuration of the LCDC.
dithering patterns used to generate gray shades or colors in these modules. They
are loaded with recommended patterns at reset, so it is not necessary to write
anything on them. They can be used to improve the image quality in the display by
tuning the patterns in each application.
take care to use it properly. Do not enable the LCD (writing a 1 in LCD_PWR field)
until the previous steps and the configuration of the DMA have been finished.
the display, when the LCDCC line is used.
register must be configured with the base address of the display buffer in memory. In
dual scan mode DMABADDR1 should be configured with the base address of the
Upper Panel display buffer and DMABADDR2 should be configured with the base
address of the Lower Panel display buffer.
the vertical size to use in the calculation is that of each panel. Respect to the
BRSTLN field, a recommended value is a 4-word burst.
been configured, enable the DMA Controller by writing a “1” to the DMAEN field of
this register. If using a dual scan module or the 2D addressing feature, do not forget
to write the DMAUPDT bit after every change to the set of DMA configuration values.
Memory Addressing” on page
922).
“FIFO” on page 902
AT91SAM9263
“2D
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