AT91SAM9263B-CU Atmel, AT91SAM9263B-CU Datasheet - Page 966
AT91SAM9263B-CU
Manufacturer Part Number
AT91SAM9263B-CU
Description
IC ARM9 MCU 200 MHZ 324-TFBGA
Manufacturer
Atmel
Series
AT91SAMr
Specifications of AT91SAM9263B-CU
Core Processor
ARM9
Core Size
16/32-Bit
Speed
240MHz
Connectivity
CAN, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
AC'97, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Size
128KB (128K x 8)
Program Memory Type
ROM
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
324-TFBGA
Processor Series
AT91SAMx
Core
ARM926EJ-S
Data Bus Width
32 bit
Data Ram Size
96 KB
Interface Type
2-Wire, EBI, I2S, MCI, SPI, USART
Maximum Clock Frequency
200 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM9263-EK
Minimum Operating Temperature
- 40 C
Package
324TFBGA
Device Core
ARM926EJ-S
Family Name
91S
Maximum Speed
200 MHz
Operating Supply Voltage
1.8|2.5|3.3 V
Controller Family/series
AT91SAM9xxx
No. Of I/o's
160
Ram Memory Size
96KB
Cpu Speed
240MHz
No. Of Timers
1
Rohs Compliant
Yes
For Use With
AT91SAM9263-EK - KIT EVAL FOR AT91SAM9263AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
Q3735625
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT91SAM9263B-CU
Manufacturer:
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Quantity:
1 043
Part Number:
AT91SAM9263B-CU
Manufacturer:
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Figure 45-11. Command Queuing
45.3.1.12
966
CPU WRITE
AT91SAM9263
Recommended Procedure for Using the Command Queue
ADDRESS = 0x08
BUF END = 64
LENGTH = 9
TDGC FIFO
SBXR
SBXR
SBYR
TEXR
TEYR
GOR
LWR
CSR
LOR
LPR
In order to optimize the small command FIFO (64 half words) use, and due to the restriction of
the APB access that has to be full word only, all 32-bit registers are split into two registers. This
only affects the clipping command where the start and end coordinates of the line to be clipped
could be outside the range of 2048 pixels and may need 32 bits to define line coordinates. Thus
extra accesses to the FIFO must be made if the clip line coordinate has to be represented in 32
bits versus 16 bits. See the specific example of clipping command that shows the change in
code as described above.
• Load the entire queue (equal to 64) with commands.
• Enable command queue buffer empty interrupt (BUFE) in TDGC_GMR if using interrupts
instead of polling.
READ FIFO
DRAW QUEUE
CONTROL
WRITE TO REG
TDGC REGISTERS
SBXR
SBYR
TEXR
TEYR
GOR
LWR
CSR
LPR
LOR
6249H–ATARM–27-Jul-09
RENDER LINE
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