AT91SAM9263B-CU Atmel, AT91SAM9263B-CU Datasheet - Page 674

IC ARM9 MCU 200 MHZ 324-TFBGA

AT91SAM9263B-CU

Manufacturer Part Number
AT91SAM9263B-CU
Description
IC ARM9 MCU 200 MHZ 324-TFBGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheets

Specifications of AT91SAM9263B-CU

Core Processor
ARM9
Core Size
16/32-Bit
Speed
240MHz
Connectivity
CAN, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
AC'97, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Size
128KB (128K x 8)
Program Memory Type
ROM
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
324-TFBGA
Processor Series
AT91SAMx
Core
ARM926EJ-S
Data Bus Width
32 bit
Data Ram Size
96 KB
Interface Type
2-Wire, EBI, I2S, MCI, SPI, USART
Maximum Clock Frequency
200 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM9263-EK
Minimum Operating Temperature
- 40 C
Package
324TFBGA
Device Core
ARM926EJ-S
Family Name
91S
Maximum Speed
200 MHz
Operating Supply Voltage
1.8|2.5|3.3 V
Controller Family/series
AT91SAM9xxx
No. Of I/o's
160
Ram Memory Size
96KB
Cpu Speed
240MHz
No. Of Timers
1
Rohs Compliant
Yes
For Use With
AT91SAM9263-EK - KIT EVAL FOR AT91SAM9263AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
Q3735625

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Figure 37-18. Consumer Handling
37.7.4
37.7.4.1
Figure 37-19. Mailbox Timestamp
6249H–ATARM–27-Jul-09
MTIMESTAMP
MTIMESTAMP
(CAN_MCRx)
(CAN_MSRx)
(CAN_MSRx)
TIMESTAMP
(CAN_TSTP)
CAN_MDHx)
(CAN_MSRx)
(CAN_MDLx
(CAN_MSRy)
(CAN_MR)
CAN BUS
CAN BUS
CAN_TIM
TEOF
MRDY
MTCR
MMI
CAN Controller Timing Modes
Timestamping Mode
Using the free running 16-bit internal timer, the CAN controller can be set in one of the two fol-
lowing timing modes:
Timestamping Mode is enabled by clearing the TTM bit in the CAN_MR register. Time Triggered
Mode is enabled by setting the TTM bit in the CAN_MR register.
Each mailbox has its own timestamp value. Each time a message is sent or received by a mail-
box, the 16-bit value MTIMESTAMP of the CAN_TIMESTP register is transferred to the LSB bits
of the CAN_MSRx register. The value read in the CAN_MSRx register corresponds to the inter-
nal timer value at the Start Of Frame or the End Of Frame of the message handled by the
mailbox.
Remote Frame
Timestamp 1
• Timestamping Mode: The value of the internal timer is captured at each Start Of Frame or
• Time Triggered Mode: The mailbox transfer operation is triggered when the internal timer
Timestamp 1
Message 1
each End Of Frame.
reaches the mailbox trigger.
Start of Frame
Message x
End of Frame
Message x
Remote Frame
Message 2
Message y
Timestamp 2
Timestamp 2
AT91SAM9263
Message y
674

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