AT91SAM9263B-CU Atmel, AT91SAM9263B-CU Datasheet - Page 675

• Manufacturer Part Number: AT91SAM9263B-CU
• Description: IC ARM9 MCU 200 MHZ 324-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9263B-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 240MHz
• Connectivity: CAN, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: 2-Wire, EBI, I2S, MCI, SPI, USART
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9263-EK
• Minimum Operating Temperature: - 40 C
• Package: 324TFBGA
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 200 MHz
• Operating Supply Voltage: 1.8|2.5|3.3 V
• Controller Family/series: AT91SAM9xxx
• No. Of I/o's: 160
• Ram Memory Size: 96KB
• Cpu Speed: 240MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• For Use With: AT91SAM9263-EK - KIT EVAL FOR AT91SAM9263AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q3735625

37.7.4.2
Figure 37-20. Time Triggered Principle
37.7.4.3
37.7.4.4
37.7.4.5
6249H–ATARM–27-Jul-09
Reference
Message
Time Triggered Mode
Synchronization by a Reference Message
Transmitting within a Time Window
Freezing the Internal Timer Counter
In Time Triggered Mode, basic cycles can be split into several time windows. A basic cycle starts
with a reference message. Each time a window is defined from the reference message, a trans-
mit operation should occur within a pre-defined time window. A mailbox must not win the
arbitration in a previous time window, and it must not be retried if the arbitration is lost in the time
window.
Time Trigger Mode is enabled by setting the TTM field in the CAN_MR register. In Time Trig-
gered Mode, as in Timestamp Mode, the CAN_TIMESTP field captures the values of the internal
counter, but the MTIMESTAMP fields in the CAN_MSRx registers are not active and are read at
0.
In Time Triggered Mode, the internal timer counter is automatically reset when a new message
is received in the last mailbox. This reset occurs after the reception of the End Of Frame on the
rising edge of the MRDY signal in the CAN_MSRx register. This allows synchronization of the
internal timer counter with the reception of a reference message and the start a new time
window.
A time mark is defined for each mailbox. It is defined in the 16-bit MTIMEMARK field of the
CAN_MMRx register. At each internal timer clock cycle, the value of the CAN_TIM is compared
with each mailbox time mark. When the internal timer counter reaches the MTIMEMARK value,
an internal timer event for the mailbox is generated for the mailbox.
In Time Triggered Mode, transmit operations are delayed until the internal timer event for the
mailbox. The application prepares a message to be sent by setting the MTCR in the CAN_MCRx
register. The message is not sent until the CAN_TIM value is less than the MTIMEMARK value
defined in the CAN_MMRx register.
If the transmit operation is failed, i.e., the message loses the bus arbitration and the next trans-
mit attempt is delayed until the next internal time trigger event. This prevents overlapping the
next time window, but the message is still pending and is retried in the next time window when
CAN_TIM value equals the MTIMEMARK value. It is also possible to prevent a retry by setting
the DRPT field in the CAN_MR register.
The internal counter can be frozen by setting TIMFRZ in the CAN_MR register. This prevents an
unexpected roll-over when the counter reaches FFFFh. When this occurs, it automatically
freezes until a new reset is issued, either due to a message received in the last mailbox or any
other reset counter operations. The TOVF bit in the CAN_SR register is set when the counter is
Time Cycle
Time Windows for Messages
Global Time
Reference
Message
AT91SAM9263
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