AT91SAM9263B-CU Atmel, AT91SAM9263B-CU Datasheet - Page 1091

• Manufacturer Part Number: AT91SAM9263B-CU
• Description: IC ARM9 MCU 200 MHZ 324-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9263B-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 240MHz
• Connectivity: CAN, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: 2-Wire, EBI, I2S, MCI, SPI, USART
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9263-EK
• Minimum Operating Temperature: - 40 C
• Package: 324TFBGA
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 200 MHz
• Operating Supply Voltage: 1.8|2.5|3.3 V
• Controller Family/series: AT91SAM9xxx
• No. Of I/o's: 160
• Ram Memory Size: 96KB
• Cpu Speed: 240MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• For Use With: AT91SAM9263-EK - KIT EVAL FOR AT91SAM9263AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q3735625

6249H–ATARM–27-Jul-09
Revision
6249E
Comments (Continued)
SDRAMC:
Section 23.6.1 ”SDRAMC Mode
SDRAMC Configuration Register
SHDWC:
Table 18-1, ”Shutdown Controller Block
SMC:
Section 22.14 ”Programmable IO
Section 22.8.5 ”Coding Timing
Table 22-4 on page
Section 22.9.3.1 ”User
added.
SPI:
Section 32.7.9 ”SPI Chip Select
BITS bitfield description and
SSC:
Section 35.8.3 ”SSC Receive Clock Mode
TC:
Section 39.6 ”Timer Counter (TC) User
channel registers indexed and referenced in the register tables that follow. Functional value of WAVE is given.
Section 39.6.2 ”TC Block Mode
Section 39.6.4 ”TC Channel Mode Register: Capture
TDGC:
All mention of Polygon Fill feature removed. Fill Control Register, Vertex X, Vertex Y registers removed from
User Interface, addresses reassigned as “Reserved” in,
User Interface: 2D Graphics Controller (2DGC) replaced by Two D Graphics Controller (TDGC).
Section 45.5.23 ”VRAM Size
Section 45.5.4 ”Source/Begin Y
Section 45.5.15 ”Extended End Y
Table title number removed from tables in bitfield descriptions.
TWI:
Section 33. ”Two-wire Interface
205.
Procedure”, Instructions regarding configuration parameters of SMC Chip Select
Section 32.6.4 ”SPI Slave Mode”
Register”, VSIZE field (updated with explicit hex radix).
Parameters”, “Effective Value” column under “Permitted Range” updated in
Register”, typo fixed in bit fields 2 and 3.
(TWI)”, the implementation of the TWI has been updated in this product.
Register”, note pertaining to BITS field added. This note is referenced in the
Register”, typo “YCOR” fixed, = “YSRC”.
Register”; changed MODE bit description.
“CAS: CAS Latency” on page
Delays”, added to datasheet
Register”, typo EXT_BY fixed, = “EXT_EY”.
Interface”, Register mapping consolidated into one table, offsets of
Diagram”; corrected register names in the block diagram.
Register”, corrected bit name to STTDLY.
Mode”, bit field 15 updated.
Table 45-2, “TDGC Register Mapping,” on page
250, changed CAS bit description
AT91SAM9263
971.
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