AT91SAM9263B-CU Atmel, AT91SAM9263B-CU Datasheet - Page 298

• Manufacturer Part Number: AT91SAM9263B-CU
• Description: IC ARM9 MCU 200 MHZ 324-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9263B-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 240MHz
• Connectivity: CAN, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: 2-Wire, EBI, I2S, MCI, SPI, USART
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9263-EK
• Minimum Operating Temperature: - 40 C
• Package: 324TFBGA
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 200 MHz
• Operating Supply Voltage: 1.8|2.5|3.3 V
• Controller Family/series: AT91SAM9xxx
• No. Of I/o's: 160
• Ram Memory Size: 96KB
• Cpu Speed: 240MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• For Use With: AT91SAM9263-EK - KIT EVAL FOR AT91SAM9263AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q3735625

25.3.6
25.3.6.1
298
AT91SAM9263
Disabling a Channel Prior to Transfer Completion
Abnormal Transfer Termination
Under normal operation, software enables a channel by writing a ‘1’ to the Channel Enable Reg-
ister, DMAC_ChEnReg.CH_EN, and hardware disables a channel on transfer completion by
clearing the DMAC_ChEnReg.CH_EN register bit.
The recommended way for software to disable a channel without losing data is to use the
CH_SUSP bit in conjunction with the FIFO_EMPTY bit in the Channel Configuration Register
(DMAC_CFGx) register.
When DMAC_CTLx.SRC_TR_WIDTH is less than DMAC_CTLx.DST_TR_WIDTH and the
DMAC_CFGx.CH_SUSP bit is high, the DMAC_CFGx.FIFO_EMPTY is asserted once the con-
tents of the FIFO do not permit a single word of DMAC_CTLx.DST_TR_WIDTH to be formed.
However, there may still be data in the channel FIFO but not enough to form a single transfer of
DMAC_CTLx.DST_TR_WIDTH width. In this configuration, once the channel is disabled, the
remaining data in the channel FIFO are not transferred to the destination peripheral. It is permit-
t e d t o r e m o v e t h e c h a n n e l f r o m t h e s u s p e n s i o n s t a t e b y w r i t i n g a ‘ 0 ’ t o t h e
DMAC_CFGx.CH_SUSP register. The DMA transfer completes in the normal manner.
Note:
A DMAC DMA transfer may be terminated abruptly by software by clearing the channel enable
bit, DMAC_ChEnReg.CH_EN. This does not mean that the channel is disabled immediately
after the DMAC_ChEnReg.CH_EN bit is cleared over the AHB slave interface. Consider this as
a request to disable the channel. The DMAC_ChEnReg.CH_EN must be polled and then it must
be confirmed that the channel is disabled by reading back 0. A case where the channel is not be
disabled after a channel disable request is where either the source or destination has received a
split or retry response. The DMAC must keep re-attempting the transfer to the system HADDR
that originally received the split or retry response until an OKAY response is returned. To do oth-
erwise is an AMBA protocol violation.
Software may terminate all channels abruptly by clearing the global enable bit in the DMAC Con-
figuration Register (DMAC_DmaCfgReg[0]). Again, this does not mean that all channels are
disabled immediately after the DMAC_DmaCfgReg[0] is cleared over the AHB slave interface.
Consider this as a request to disable all channels. The DMAC_ChEnReg must be polled and
then it must be confirmed that all channels are disabled by reading back ‘0’.
Note:
Note:
1. If software wishes to disable a channel prior to the DMA transfer completion, then it can
2. Software can now poll the DMAC_CFGx.FIFO_EMPTY bit until it indicates that the
3. The DMAC_ChEnReg.CH_EN bit can then be cleared by software once the channel
set the DMAC_CFGx.CH_SUSP bit to tell the DMAC to halt all transfers from the
source peripheral. Therefore, the channel FIFO receives no new data.
channel FIFO is empty.
FIFO is empty.
If a channel is disabled by software, an active single or burst transaction is not guaranteed to
receive an acknowledgement.
If the channel enable bit is cleared while there is data in the channel FIFO, this data is not sent to
the destination peripheral and is not present when the channel is re-enabled. For read sensitive
source peripherals such as a source FIFO this data is therefore lost. When the source is not a
read sensitive device (i.e., memory), disabling a channel without waiting for the channel FIFO to
empty may be acceptable as the data is available from the source peripheral upon request and is
not lost.
If a channel is disabled by software, an active single or burst transaction is not guaranteed to
receive an acknowledgement.
6249H–ATARM–27-Jul-09