AT91SAM9263B-CU Atmel, AT91SAM9263B-CU Datasheet
AT91SAM9263B-CU
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AT91SAM9263B-CU Summary of contents
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Features ™ • Incorporates the ARM926EJ-S – DSP Instruction Extensions, Jazelle – 16 Kbyte Data Cache, 16 Kbyte Instruction Cache, Write Buffer – 220 MIPS at 200 MHz – Memory Management Unit ™ – EmbeddedICE , Debug Communication Channel Support ...
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... Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel – Double PWM Generation, Capture/Waveform Mode, Up/Down Capability • One Four-channel 16-bit PWM Controller (PWMC) • One Two-wire Interface (TWI) – Master Mode Support, All Two-wire Atmel AT91SAM9263 2 ™ Compliant ® ...
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IEEE 1149.1 JTAG Boundary Scan on All Digital Pins • Required Power Supplies – 1.08V to 1.32V for VDDCORE and VDDBU – 3.0V to 3.6V for VDDOSC and VDDPLL – 2.7V to 3.6V for VDDIOP0 (Peripheral I/Os) – ...
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AT91SAM9263 Block Diagram Figure 2-1. AT91SAM9263 Block Diagram AT91SAM9263 4 6249H–ATARM–27-Jul-09 ...
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Signal Description Table 3-1 Table 3-1. Signal Description List Signal Name Function VDDIOM0 EBI0 I/O Lines Power Supply VDDIOM1 EBI1 I/O Lines Power Supply VDDIOP0 Peripherals I/O Lines Power Supply VDDIOP1 Peripherals I/O Lines Power Supply VDDBU Backup I/O ...
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Table 3-1. Signal Description List (Continued) Signal Name Function TSYNC Trace Synchronization Signal TCLK Trace Clock TPS0 - TPS2 Trace ARM Pipeline Status TPK0 - TPK15 Trace Packet Port NRST Microcontroller Reset TST Test Mode Select BMS Boot Mode Select ...
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Table 3-1. Signal Description List (Continued) Signal Name Function EBI0_CFCE1 - EBI0_CFCE2 CompactFlash Chip Enable EBI0_CFOE CompactFlash Output Enable EBI0_CFWE CompactFlash Write Enable EBI0_CFIOR CompactFlash IO Read EBI0_CFIOW CompactFlash IO Write EBI0_CFRNW CompactFlash Read Not Write EBI0_CFCS0 - EBI0_CFCS1 CompactFlash ...
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Table 3-1. Signal Description List (Continued) Signal Name Function TKx SSCx Transmit Clock RKx SSCx Receive Clock TFx SSCx Transmit Frame Sync RFx SSCx Receive Frame Sync AC97RX AC97 Receive Signal AC97TX AC97 Transmit Signal AC97FS AC97 Frame Synchronization Signal ...
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Table 3-1. Signal Description List (Continued) Signal Name Function ETXCK Transmit Clock or Reference Clock ERXCK Receive Clock ETXEN Transmit Enable ETX0-ETX3 Transmit Data ETXER Transmit Coding Error ERXDV Receive Data Valid ERX0-ERX3 Receive Data ERXER Receive Error ECRS Carrier ...
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Package and Pinout The AT91SAM9263 is available in a 324-ball TFBGA Green package mm, 0.8mm ball pitch. 4.1 324-ball TFBGA Package Outline Figure 4-1 A detailed mechanical description is given in the section “AT91SAM9263 Mechanical Character- ...
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TFBGA Package Pinout Table 4-1. AT91SAM9263 Pinout for 324-ball TFBGA Package Pin Signal Name Pin A1 EBI0_D2 E10 A2 EBI0_SDCKE E11 A3 EBI0_NWE_NWR0 E12 A4 EBI0_NCS1_SDCS E13 A5 EBI0_A19 E14 A6 EBI0_A11 E15 A7 EBI0_A10 E16 A8 EBI0_A5 ...
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Table 4-1. AT91SAM9263 Pinout for 324-ball TFBGA Package (Continued) Pin Signal Name Pin C15 PC3 H6 C16 GND H7 C17 VDDIOP0 H8 C18 HDPB H9 D1 EBI0_D10 H10 D2 EBI0_D3 H11 ( H12 D4 EBI0_D1 H13 D5 EBI0_A20 ...
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Power Considerations 5.1 Power Supplies AT91SAM9263 has several types of power supply pins: • VDDCORE pins: Power the core, including the processor, the embedded memories and the peripherals; voltage ranges from 1.08V to 1.32V, 1.2V nominal. • VDDIOM0 and ...
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EBI0 voltage range. The user must be sure to program the EBI0 voltage range before getting the device out of its Slow Clock Mode. 6. I/O Line Considerations 6.1 JTAG Port Pins ...
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MΩ. The resistor value is calculated according to the regulator enable implementation and the SHDN level. The pin WKUP is an input-only. It can accept voltages only between 0V and VDDBU. 7. Processor and Architecture 7.1 ARM926EJ-S Processor • RISC ...
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Bus Matrix • 9-layer Matrix, handling requests from 9 masters • Programmable Arbitration strategy – Fixed-priority Arbitration – Round-Robin Arbitration, either with no default master, last accessed default master • Burst Management – Breaking with Slot Cycle Limit Support ...
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The LCD Controller, the DMA Controller, the USB OTG and the USB Host have a user interface mapped as a slave on the Matrix. They share the same layer, as programming them does not require a high bandwidth. Table 7-2. ...
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Master to Slave Access In most cases, all the masters can access all the slaves. However, some paths do not make sense, for example, allowing access from the Ethernet MAC to the Internal Peripherals. Thus, these paths are forbidden ...
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USART1 Transmit Channel – USART0 Transmit Channel – AC97 Transmit Channel – SPI1 Transmit Channel – SPI0 Transmit Channel – SSC1 Transmit Channel – SSC0 Transmit Channel – DBGU Receive Channel – USART2 Receive Channel – USART1 Receive Channel ...
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Suspend DMA operation – Programmable DMA lock transfer support. • Transfer Initiation – Supports four external DMA Requests – Support for software handshaking interface. Memory mapped registers can be used • Interrupt – Programmable interrupt generation on DMA transfer ...
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Memories Figure 8-1. AT91SAM9263 Memory Mapping Address Memory Space 0x0000 0000 Internal Memories 0x0FFF FFFF 0x1000 0000 EBI0 Chip Select 0 0x1FFF FFFF 0x2000 0000 EBI0 Chip Select 1/ EBI0 SDRAMC 0x2FFF FFFF 0x3000 0000 EBI0 Chip Select 2 ...
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A first level of address decoding is performed by the Bus Matrix, i.e., the implementation of the Advanced High Performance Bus (AHB) for its master and slave interfaces with additional features. Decoding breaks up the 4G bytes of address space ...
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Chip Configuration User Interface. This SRAM block is also accessible by the ARM926 Data Master and by the AHB Masters through the AHB bus at address 0x0010 0000. • Internal SRAM B is the ARM926EJ-S ...
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Table 8-3. 16 Kbyte Block Allocation (Continued) Configuration examples and related 16 Kbyte block assignments ITCM = 0 Kbyte Decoded DTCM = 0 Kbyte Area Address AHB = 80 Kbytes 0x0030 0000 0x0030 4000 Internal SRAM C 0x0030 8000 (AHB) ...
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SD Card – NAND Flash – SPI DataFlash • Interface with SAM-BA – Serial communication on a DBGU – USB Bulk Device Port 8.1.2.2 BMS = 0, Boot on External Memory • Boot at slow clock • Boot with ...
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External Bus Interface 1 • Integrates three External Memory Controllers: – Static Memory Controller – SDRAM Controller – ECC Controller • Additional logic for NAND Flash • Optional Full 32-bit External Data Bus • 23-bit Address Bus ...
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Energy-saving capabilities – Self-refresh, power down and deep power down modes supported • Error detection – Refresh Error Interrupt • SDRAM Power-up Initialization by software • CAS Latency and 3 supported • Auto Precharge Command not ...
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System Controller Block Diagram Figure 9-1. AT91SAM9263 System Controller Block Diagram irq0-irq1 periph_irq[2..29] pit_irq rtt0_irq rtt1_irq wdt_irq dbgu_irq pmc_irq rstc_irq periph_nreset dbgu_rxd debug periph_nreset SLCK debug proc_nreset NRST VDDCORE POR VDDCORE VDDBU VDDBU POR SLCK SLCK backup_nreset SLCK backup_nreset ...
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Reset Controller • Based on two Power-on-Reset cells – One on VDDBU and one on VDDCORE • Status of the last reset – Either general reset (VDDBU rising), wake-up reset (VDDCORE rising), software • Controls the internal resets and ...
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Power Management Controller • Provides: – the Processor Clock PCK – the Master Clock MCK, in particular to the Matrix and the memory interfaces – the USB Device Clock UDPCK – the USB Host Clock UHPCK – independent peripheral ...
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Windowed, prevents the processor deadlocking on the watchdog access 9.8 Real-time Timer • Two Real-time Timers, allowing backup of time with different accuracies – 32-bit Free-running back-up counter – Integrates a 16-bit programmable prescaler running on the embedded 32.768Hz ...
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... Implemented features are 100% compatible with the standard Atmel USART – Independent receiver and transmitter with a common programmable Baud Rate – Even, Odd, Mark or Space Parity Generation – Parity, Framing and Overrun Error Detection – Automatic Echo, Local Loopback and Remote Loopback Channel Modes – ...
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Peripherals 10.1 User Interface The Peripherals are mapped in the upper 256 Mbytes of the address space between the addresses 0xFFFA 0000 and 0xFFFC FFFF. Each User Peripheral is allocated 16 Kbytes of address space. A complete memory map ...
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Table 10-1. AT91SAM9263 Peripheral Identifiers (Continued) Peripheral ID Peripheral Mnemonic 29 UHP 30 AIC 31 AIC Note: Setting AIC, SYSC, UHP and IRQ0 - 1 bits in the clock set/clear registers of the PMC has no effect. 10.2.1 Peripheral Interrupts ...
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As a result, the bit corresponding to the PIO Line in the register PIO_PSR (Peripheral Status Register) resets low signal name is specified in the ...
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PIO Controller A Multiplexing Table 10-2. Multiplexing on PIO Controller A PIO Controller A I/O Line Peripheral A PA0 MCI0_DA0 PA1 MCI0_CDA PA2 PA3 MCI0_DA1 PA4 MCI0_DA2 PA5 MCI0_DA3 PA6 MCI1_CK PA7 MCI1_CDA PA8 MCI1_DA0 PA9 MCI1_DA1 PA10 MCI1_DA2 ...
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PIO Controller B Multiplexing Table 10-3. Multiplexing on PIO Controller B PIO Controller B I/O Line Peripheral A PB0 AC97FS PB1 AC97CK PB2 AC97TX PB3 AC97RX PB4 TWD PB5 TWCK PB6 TF1 PB7 TK1 PB8 TD1 PB9 RD1 PB10 ...
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PIO Controller C Multiplexing Table 10-4. Multiplexing on PIO Controller C PIO Controller C I/O Line Peripheral A PC0 LCDVSYNC PC1 LCDHSYNC PC2 LCDDOTCK PC3 LCDDEN PC4 LCDD0 PC5 LCDD1 PC6 LCDD2 PC7 LCDD3 PC8 LCDD4 PC9 LCDD5 PC10 ...
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PIO Controller D Multiplexing Table 10-5. Multiplexing on PIO Controller D PIO Controller D I/O Line Peripheral A PD0 TXD1 PD1 RXD1 PD2 TXD2 PD3 RXD2 PD4 FIQ PD5 EBI0_NWAIT PD6 EBI0_NCS4/CFCS0 PD7 EBI0_NCS5/CFCS1 PD8 EBI0_CFCE1 PD9 EBI0_CFCE2 PD10 ...
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PIO Controller E Multiplexing Table 10-6. Multiplexing on PIO Controller E PIO Controller E I/O Line Peripheral A PE0 ISI_D0 PE1 ISI_D1 PE2 ISI_D2 PE3 ISI_D3 PE4 ISI_D4 PE5 ISI_D5 PE6 ISI_D6 PE7 ISI_D7 PE8 ISI_PCK PE9 ISI_HSYNC PE10 ...
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System Resource Multiplexing 10.4.1 LCD Controller The LCD Controller can interface with several LCD panels. It supports 4 bits per pixel (bpp), 8 bpp or 16 bpp without limitation. Interfacing 24 bpp TFT panels prevents using the Ethernet MAC. ...
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CompactFlash Using the CompactFlash interface prevents using NCS4 and/or NCS5 to access other parallel devices. 10.4.9 SPI0 and MCI Interface SPI0 signals and MCI0 signals are multiplexed, as the DataFlash Card is hardware-compatible with the SDCard. Only one can ...
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USART • Programmable Baud Rate Generator • 9-bit full-duplex synchronous or asynchronous serial communications – stop bits in Asynchronous Mode stop bits in Synchronous Mode – Parity generation and ...
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Timer Counter • Three 16-bit Timer Counter Channels • Wide range of functions including: – Frequency Measurement – Event Counting – Interval Measurement – Pulse Generation – Delay Timing – Pulse Width Modulation – Up/down Capabilities • Each channel ...
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Bit rates up to 1Mbit/s. • Object-oriented mailboxes, each with the following properties: – CAN Specification 2.0 Part A or 2.0 Part B programmable for each message – Object Configurable as receive (with overwrite or not) or transmit – ...
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STN • bits per pixel (palletized), 16, 24 bits per pixel (non-palletized) for TFT • Single clock domain architecture • ...
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ARM926EJ-S Processor Overview 11.1 Overview The ARM926EJ-S processor is a member of the ARM9s family of general-purpose microproces- sors. The ARM926EJ-S implements ARM architecture version 5TEJ and is targeted at multi- tasking applications where full memory management, high performance, ...
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Block Diagram Figure 11-1. ARM926EJ-S Internal Functional Block Diagram ETM Interface WDATA RDATA ARM9EJ-S EmbeddedICE Processor -RT INSTR ICE Interface 11.3 ARM9EJ-S Processor ™ 11.3.1 ARM9EJ-S Operating States The ARM9EJ-S processor can operate in three different states, each with ...
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ARM state and Jazelle state using the BXJ instruction All exceptions are entered, handled and exited in ARM state exception occurs in Thumb or Jazelle states, the processor reverts to ARM state. The transition back to Thumb ...
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Supervisor mode is a protected mode for the operating system • Abort mode is entered after a data or instruction prefetch abort • System mode is a privileged user mode for the operating system • Undefined mode is entered ...
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Register r14 is used as a Link register that holds a value (return address) of r15 when BL or BLX is executed. Register r15 is used as a pro- gram counter ...
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Figure 11-2. Status Register Format Figure 11-2 • N: Negative, Z: Zero, C: Carry, and V: Overflow are the four ALU flags • The Sticky Overflow (Q) flag can be set by certain multiply and fractional arithmetic instructions like QADD, ...
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The BKPT, or Undefined instruction, and SWI exceptions are mutually exclusive. There is one exception in the priority scheme though, when FIQs are enabled and a Data Abort occurs at the same time as an FIQ, the ARM9EJ-S core enters ...
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Data processing instructions • Status register transfer instructions • Load and Store instructions • Coprocessor instructions • Exception-generating instructions ARM instructions can be executed conditionally. Every instruction contains a 4-bit condition code field (bits[31:28]). Table 11-2 Table 11-2. Mnemonic ...
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New ARM Instruction Set . Table 11-3. Mnemonic BXJ BLX SMLAxy SMLAL SMLAWy SMULxy SMULWy QADD QDADD QSUB QDSUB Notes: 11.3.10 Thumb Instruction Set Overview The Thumb instruction set is a re-encoded subset of the ARM instruction set. The ...
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Table 11-4. Mnemonic EOR LSL ASR MUL B BX LDR LDRH LDRB LDRSH LDMIA PUSH BCC 11.4 CP15 Coprocessor Coprocessor 15, or System Control Coprocessor CP15, is used to configure and control all the items in the list below: • ...
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Table 11-5. Register Notes: 6249H–ATARM–27-Jul-09 CP15 Registers Name 8 TLB operations (2) 9 cache lockdown 9 TCM region 10 TLB lockdown 11 Reserved 12 Reserved (1) 13 FCSE PID (1) 13 Context ID 14 Reserved 15 Test configuration 1. Register ...
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CP15 Registers Access CP15 registers can only be accessed in privileged mode by: • MCR (Move to Coprocessor from ARM Register) instruction is used to write an ARM register to CP15. • MRC (Move to ARM Register from Coprocessor) ...
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Memory Management Unit (MMU) The ARM926EJ-S processor implements an enhanced ARM architecture v5 MMU to provide vir- tual memory features required by operating systems like Symbian OS These virtual memory features are memory access permission controls and virtual to ...
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Translation Look-aside Buffer (TLB) The Translation Look-aside Buffer (TLB) caches translated entries and thus avoids going through the translation process every time. When the TLB contains an entry for the MVA (Modi- fied Virtual Address), the access control logic ...
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A new feature is now supported by ARM926EJ-S caches called allocate on read-miss commonly known as wrapping. This feature enables the caches to perform critical word first cache refilling. This means that when a request for a word causes a ...
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The DCache contains an eight data word entry, single address entry write-back buffer used to hold write-back data for cache line eviction or cleaning of dirty cache lines. The Write Buffer can hold words of data and ...
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... The ARM926EJ-S processor performs all AHB accesses as single word, bursts of four words, or bursts of eight words. Any ARM9EJ-S core request that is not words in size is split into packets of these sizes. Note that the Atmel bus is AHB-Lite protocol compliant, hence it does not support split and retry requests. ...
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Table 11-7. Supported Transfers HBurst[2:0] Description SINGLE Single transfer INCR4 Four-word incrementing burst INCR8 Eight-word incrementing burst WRAP8 Eight-word wrapping burst 11.8.2 Thumb Instruction Fetches All instructions fetches, regardless of the state of ARM9EJ-S core, are made as 32-bit accesses ...
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AT91SAM9263 Debug and Test 12.1 Overview The AT91SAM9263 features a number of complementary debug and test capabilities. A com- mon JTAG/ICE (In-Circuit Emulator) port is used for standard debugging functions, such as downloading code and single-stepping through programs. An ...
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Block Diagram Figure 12-1. Debug and Test Block Diagram TAP: Test Access Port AT91SAM9263 66 ICE/JTAG Boundary TAP Port ARM9EJ-S ICE-RT ETM ARM926EJ-S PDC DBGU TMS TCK TDI NTRST JTAGSEL TDO RTCK POR Reset and TST Test TPK0-TPK15 TPS0-TPS2 ...
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Application Examples 12.3.1 Debug Environment Figure 12-2 on page 67 face is used for standard debugging functions, such as downloading code and single-stepping through the program. The Trace Port interface is used for tracing information. A software debug- ger ...
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Debug and Test Pin Description Table 12-1. Pin Name NTRST NRST TST TCK TDI TDO TMS RTCK JTAGSEL TSYNC TCLK TPS0 - TPS2 TPK0 - TPK15 DRXD DTXD 12.5 Functional Description 12.5.1 Test Pin One dedicated pin, TST, is ...
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... JTAG registers) and propagates them to the next chip in the serial test circuit. NTRST (optional in IEEE Standard 1149. Test-ReSeT input which is mandatory in ARM cores and used to reset the debug logic. On Atmel ARM926EJ-S-based cores, NTRST is a Power On Reset output asserted on power on. If necessary, the user can also reset the debug logic with the NTRST pin assertion during 2 ...
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Embedded Trace Macrocell The AT91SAM9263 features an Embedded Trace Macrocell (ETM), which is closely connected to the ARM926EJ-S Processor. The Embedded Trace is a standard Medium+ level implementa- tion and contains the following resources: • Four pairs of address ...
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Figure 12-4. ETM9 Block 12.5.5.2 Implementation Details This section gives an overview of the Embedded Trace resources. Three-state Sequencer The sequencer has three possible next states (one dedicated to itself and two others) and can change on every clock cycle. ...
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Memory Decoder Inputs The eight memory map decoder inputs are connected to custom address decoders. The address decoders divide the memory into regions of on-chip SRAM, on-chip ROM, and peripher- als. The address decoders also optimize the ETM9 trace trigger. ...
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Application Board Restriction The TCLK signal needs to be set with care, some timing parameters are required. See “ETM Timings” for more details. The specified target system connector is the AMP Mictor connector. The connector must be oriented on ...
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Each AT91SAM9263 input/output pin corresponds to a 3-bit register in the BSR. The OUTPUT bit contains data that can be forced on the pad. The INPUT bit facilitates the observability of data applied to the pad. The CONTROL bit selects ...
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Table 12-3. Bit Number 633 632 631 630 629 628 627 626 625 624 623 622 621 620 619 618 617 616 615 614 613 612 611 610 609 608 607 606 605 604 603 602 601 600 599 6249H–ATARM–27-Jul-09 ...
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Table 12-3. Bit Number 598 597 596 595 594 593 592 591 590 589 588 587 586 585 584 583 582 581 580 579 578 577 576 575 574 573 572 571 570 569 568 567 566 565 564 AT91SAM9263 ...
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Table 12-3. Bit Number 563 562 561 560 559 558 557 556 555 554 553 552 551 550 549 548 547 546 545 544 543 542 541 540 539 538 537 536 535 534 533 532 531 6249H–ATARM–27-Jul-09 AT91SAM9263 JTAG ...
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Table 12-3. Bit Number 530 529 528 527 526 525 524 523 522 521 520 519 518 517 516 515 514 513 512 511 510 509 508 507 506 505 504 503 502 501 500 499 498 497 496 AT91SAM9263 ...
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Table 12-3. Bit Number 495 494 493 492 491 490 489 488 487 486 485 484 483 482 481 480 479 478 477 476 475 474 473 472 471 470 469 468 467 466 465 464 463 6249H–ATARM–27-Jul-09 AT91SAM9263 JTAG ...
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Table 12-3. Bit Number 462 461 460 459 458 457 456 455 454 453 452 451 450 449 448 447 446 445 444 443 442 441 440 439 438 437 436 435 434 433 432 431 430 AT91SAM9263 80 AT91SAM9263 ...
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Table 12-3. Bit Number 429 428 427 426 425 424 423 422 421 420 419 418 417 416 415 414 413 412 411 410 409 408 407 406 405 404 403 402 401 400 399 398 397 6249H–ATARM–27-Jul-09 AT91SAM9263 JTAG ...
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Table 12-3. Bit Number 396 395 394 393 392 391 390 389 388 387 386 385 384 383 382 381 380 379 378 377 376 375 374 373 372 371 370 369 368 367 366 365 364 AT91SAM9263 82 AT91SAM9263 ...
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Table 12-3. Bit Number 363 362 361 360 359 358 357 356 355 354 353 352 351 350 349 348 347 346 345 344 343 342 341 340 339 338 337 336 335 334 333 332 331 6249H–ATARM–27-Jul-09 AT91SAM9263 JTAG ...
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Table 12-3. Bit Number 330 329 328 327 326 325 324 323 322 321 320 319 318 317 316 315 314 313 312 311 310 309 308 307 306 305 304 303 302 301 300 299 298 AT91SAM9263 84 AT91SAM9263 ...
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Table 12-3. Bit Number 297 296 295 294 293 292 291 290 289 288 287 286 285 284 283 282 281 280 279 278 277 276 275 274 273 272 271 270 269 268 267 266 265 6249H–ATARM–27-Jul-09 AT91SAM9263 JTAG ...
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Table 12-3. Bit Number 264 263 262 261 260 259 258 257 256 255 254 253 252 251 250 249 248 247 246 245 244 243 242 241 240 239 238 237 236 235 234 233 232 231 230 AT91SAM9263 ...
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Table 12-3. Bit Number 229 228 227 226 225 224 223 222 221 220 219 218 217 216 215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200 199 198 197 196 195 6249H–ATARM–27-Jul-09 ...
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Table 12-3. Bit Number 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 AT91SAM9263 88 AT91SAM9263 ...
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Table 12-3. Bit Number 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 6249H–ATARM–27-Jul-09 AT91SAM9263 JTAG ...
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Table 12-3. Bit Number 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 AT91SAM9263 90 AT91SAM9263 ...
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Table 12-3. Bit Number 6249H–ATARM–27-Jul-09 AT91SAM9263 JTAG ...
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Table 12-3. Bit Number AT91SAM9263 92 AT91SAM9263 ...
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Table 12-3. Bit Number 6249H–ATARM–27-Jul-09 AT91SAM9263 JTAG Boundary Scan Register ...
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ID Code Register Access: Read-only 31 30 VERSION PART NUMBER 7 6 • MANUFACTURER IDENTITY[11:1] Set to 0x01F. Bit[0] Required by IEEE Std. 1149.1. Set to 0x1. JTAG ID Code value is 0x05B0_C03F. • PART ...
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AT91SAM9263 Boot Program 13.1 Overview The Boot Program integrates different programs permitting download and/or upload into the dif- ferent memories of the product. First, it initializes the Debug Unit serial port (DBGU) and the USB Device Port. Then the ...
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Figure 13-1. Boot Program Algorithm Flow Diagram Start Main Oscillator Bypass Yes Input Frequency Table SD Card Boot No Timeout < NandFlash Boot No Timeout < SPI DataFlash Boot No Timeout < USB Enumeration ...
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Device Initialization Initialization follows the steps described below: 1. Stack setup for ARM supervisor mode 2. External Clock Detection 3. Switch Master Clock on Main Oscillator 4. C variable initialization 5. Main oscillator frequency detection 6. PLL setup: PLLB ...
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Figure 13-2. Remap Action after Download Completion 13.4 DataFlash Boot The DataFlash Boot program searches for a valid application in the SPI DataFlash memory valid application is found, this application is loaded into internal SRAM and executed by ...
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... Thus the user must replace this vector by the correct vector for his application. 13.4.3 DataFlash Boot Sequence The DataFlash boot program performs device initialization followed by the download procedure. The DataFlash boot program supports all Atmel DataFlash devices. parameters to include in the ARM vector 6 for all devices. Table 13-2. Device ...
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The DataFlash has a Status Register that determines all the parameters required to access the device. The DataFlash boot is configured to be compatible with the future design of the DataFlash. Figure 13-6. Serial DataFlash Download 6249H–ATARM–27-Jul-09 Start Send status ...
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SD Card Boot The SD Card Boot program searches for a valid application in the SD Card memory. (Boot ROM does not support high capacity SDCards.) It looks for a boot.bin file in the root directory of a FAT12/16/32 ...
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Read commands: Read a byte (o), a halfword ( word (w) from the target. – Address: Address in hexadecimal – Output: The byte, halfword or word read in hexadecimal following by ‘>’ • Send a file (S): ...
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... On Windows systems, the INF files contain the correspondence between vendor ID and product ID. Atmel provides an INF example to see the device as a new serial port and also provides another custom driver used by the SAM-BA application: atm6124.sys. Refer to the document “USB Basic Application” ...
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Table 13-4. Request GET_STATUS SET_FEATURE CLEAR_FEATURE The device also handles some class requests defined in the CDC class. Table 13-5. Request SET_LINE_CODING GET_LINE_CODING SET_CONTROL_LINE_STATE Unhandled requests are STALLed. 13.7.3.2 Communication Endpoints There are two communication endpoints and endpoint 0 is ...
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Hardware and Software Constraints • SAM-BA boot disposes of two blocks of internal SRAM. The first block is available for user code. Its size is 73728 bytes. The second block is used for variables and stacks. Table 13-6. Start ...
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Table 13-7. Peripheral SPI0 SPI0 SPI0 PIOD DBGU DBGU AT91SAM9263 106 Pins Driven during Boot Program Execution (Continued) Pin MISO SPCK NPCS0 NANDCS DRXD DTXD PIO Line PIOA0 PIOA2 PIOA5 PIOD15 PIOC30 PIOC31 6249H–ATARM–27-Jul-09 ...
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Reset Controller (RSTC) 14.1 Overview The Reset Controller (RSTC), based on power-on reset cells, handles all the resets of the sys- tem without any external components. It reports which reset occurred last. The Reset Controller also drives independently or ...
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Functional Description 14.3.1 Reset Controller Overview The Reset Controller is made NRST Manager, a Startup Counter and a Reset State Manager. It runs at Slow Clock and generates the following reset signals: • proc_nreset: Processor reset ...
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The level of the pin NRST can be read at any time in the bit NRSTL (NRST level) in RSTC_SR. As soon as the pin NRST is asserted, the bit URSTS in RSTC_SR is set. This bit clears only when ...
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Reset States The Reset State Manager handles the different reset sources and generates the internal reset signals. It reports the reset status in the field RSTTYP of the Status Register (RSTC_SR). The update of the field RSTTYP is performed ...
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Wake-up Reset The Wake-up Reset occurs when the Main Supply is down. When the Main Supply POR output is active, all the reset signals are asserted except backup_nreset. When the Main Supply pow- ers up, the POR output is ...
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User Reset The User Reset is entered when a low level is detected on the NRST pin and the bit URSTEN in RSTC_MR The NRST input signal is resynchronized with SLCK to insure proper behav- ior ...
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Except for Debug purposes, PERRST must always be used in conjunction with PROCRST (PERRST and PROCRST set both at 1 simultaneously.) • EXTRST: Writing EXTRST at 1 asserts low the NRST pin during a time defined by the ...
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Watchdog Reset The Watchdog Reset is entered when a watchdog fault occurs. This state lasts 3 Slow Clock cycles. When in Watchdog Reset, assertion of the reset signals depends on the WDRPROC bit in WDT_MR: • If WDRPROC is ...
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Reset State Priorities The Reset State Manager manages the following priorities between the different reset sources, given in descending order: • Backup Reset • Wake-up Reset • Watchdog Reset • Software Reset • User Reset Particular cases are listed ...
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Figure 14-9. Reset Controller Status and Interrupt MCK Peripheral Access 2 cycle resynchronization NRST NRSTL URSTS rstc_irq if (URSTEN = 0) and (URSTIEN = 1) AT91SAM9263 116 read RSTC_SR 2 cycle resynchronization 6249H–ATARM–27-Jul-09 ...
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Reset Controller (RSTC) User Interface Table 14-1. Register Mapping Offset Register 0x00 Control Register 0x04 Status Register 0x08 Mode Register Note: 1. The reset value of RSTC_SR either reports a General Reset or a Wake-up Reset depending on last ...
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Reset Controller Control Register Name: RSTC_CR Address: 0xFFFFFD00 Access Type:Write-only – – – – – – • PROCRST: Processor Reset effect KEY is correct, resets ...
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Reset Controller Status Register Name: RSTC_SR Address: 0xFFFFFD04 Access Type:Read-only 31 30 – – – – – – – – • URSTS: User Reset Status high-to-low edge on NRST happened ...
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Reset Controller Mode Register Name: RSTC_MR Address: 0xFFFFFD08 Access Type:Read-write – – – – – – • URSTEN: User Reset Enable 0 = The detection of a low level on the ...
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Real-Time Timer (RTT) 15.1 Description The Real-time Timer is built around a 32-bit counter and used to count elapsed seconds. It gen- erates a periodic interrupt and/or triggers an alarm on a programmed value. 15.2 Block Diagram Figure 15-1. ...
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The Real-time Timer value (CRTV) can be read at any time in the register RTT_VR (Real-time Value Register). As this value can be updated asynchronously from the Master Clock advis- able to read this register twice at the ...
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Real-time Timer (RTT) User Interface Table 15-1. Register Mapping Offset Register 0x00 Mode Register 0x04 Alarm Register 0x08 Value Register 0x0C Status Register 6249H–ATARM–27-Jul-09 Name Access RTT_MR Read-write RTT_AR Read-write RTT_VR Read-only RTT_SR Read-only AT91SAM9263 Reset 0x0000_8000 0xFFFF_FFFF 0x0000_0000 ...
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Real-time Timer Mode Register Register Name: RTT_MR Addresses: 0xFFFFFD20 (0), 0xFFFFFD50 (1) Access Type: Read/Write 31 30 – – – – • RTPRES: Real-time Timer Prescaler Value Defines the number of SLCK periods ...
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Real-time Timer Alarm Register Register Name: RTT_AR Addresses: 0xFFFFFD24 (0), 0xFFFFFD54 (1) Access Type: Read/Write • ALMV: Alarm Value Defines the alarm value (ALMV+1) compared with the Real-time Timer. 15.4.3 Real-time ...
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Real-time Timer Status Register Register Name: RTT_SR Addresses: 0xFFFFFD2C (0), 0xFFFFFD5C (1) Access Type: Read-only 31 30 – – – – – – – – • ALMS: Real-time Alarm Status 0 = The ...
Page 127
Periodic Interval Timer (PIT) 16.1 Overview The Periodic Interval Timer (PIT) provides the operating system’s scheduler interrupt designed to offer maximum accuracy and efficient management, even for systems with long response time. 16.2 Block Diagram Figure 16-1. ...
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Functional Description The Periodic Interval Timer aims at providing periodic interrupts for use by operating systems. The PIT provides a programmable overflow counter and a reset-on-read feature built around two counters: a 20-bit CPIV counter and a ...
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Figure 16-2. Enabling/Disabling PIT with PITEN 15 MCK Prescaler 0 PITEN CPIV 0 PICNT PITS (PIT_SR) APB Interface 6249H–ATARM–27-Jul-09 MCK 1 PIV - 1 PIV 1 0 read PIT_PIVR AT91SAM9263 APB cycle APB cycle restarts MCK Prescaler ...
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Periodic Interval Timer (PIT) User Interface Table 16-1. Register Mapping Offset Register 0x00 Mode Register 0x04 Status Register 0x08 Periodic Interval Value Register 0x0C Periodic Interval Image Register AT91SAM9263 130 Name Access PIT_MR Read-write PIT_SR Read-only PIT_PIVR Read-only PIT_PIIR ...
Page 131
Periodic Interval Timer Mode Register Register Name:PIT_MR Address: 0xFFFFFD30 Access Type: Read/Write 31 30 – – – – • PIV: Periodic Interval Value Defines the value compared with the primary 20-bit counter of ...
Page 132
Periodic Interval Timer Status Register Register Name: PIT_SR Address: 0xFFFFFD34 Access Type: Read-only 31 30 – – – – – – – – • PITS: Periodic Interval Timer Status 0 = The Periodic ...
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Periodic Interval Timer Value Register Register Name: PIT_PIVR Address: 0xFFFFFD38 Access Type: Read-only PICNT Reading this register clears PITS in PIT_SR. • CPIV: Current Periodic Interval Value Returns the current value ...
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Periodic Interval Timer Image Register Register Name: PIT_PIIR Address: 0xFFFFFD3C Access Type: Read-only PICNT • CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer. • PICNT: ...
Page 135
Watchdog Timer (WDT) 17.1 Overview The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It features a 12-bit down counter that allows a watchdog period seconds ...
Page 136
Functional Description The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock supplied with VDDCORE. It restarts with initial values on processor reset. The Watchdog is built around a ...
Page 137
Figure 17-2. Watchdog Behavior FFF Normal behavior WDV Forbidden Window WDD Permitted Window 0 Watchdog Fault AT91SAM9263 137 Watchdog Error WDT_CR = WDRSTT Watchdog Underflow if WDRSTEN WDRSTEN is 0 6249H–ATARM–27-Jul-09 ...
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Watchdog Timer (WDT) User Interface Table 17-1. Register Mapping Offset Register 0x00 Control Register 0x04 Mode Register 0x08 Status Register AT91SAM9263 138 Name Access WDT_CR Write-only WDT_MR Read-write Once WDT_SR Read-only Reset - 0x3FFF_2FFF 0x0000_0000 6249H–ATARM–27-Jul-09 ...
Page 139
Watchdog Timer Control Register Register Name:WDT_CR Address: 0xFFFFFD40 Access Type: Write-only – – – – – – • WDRSTT: Watchdog Restart 0: No effect. 1: Restarts the Watchdog. • KEY: Password ...
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Watchdog Timer Mode Register Register Name: WDT_MR Address: 0xFFFFFD44 Access Type: Read-write Once 31 30 WDIDLEHLT WDDIS WDRPROC WDRSTEN 7 6 • WDV: Watchdog Counter Value Defines the value loaded in the 12-bit Watchdog Counter. ...
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WDDIS: Watchdog Disable 0: Enables the Watchdog Timer. 1: Disables the Watchdog Timer. AT91SAM9263 141 6249H–ATARM–27-Jul-09 ...
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Watchdog Timer Status Register Register Name: WDT_SR Address: 0xFFFFFD48 Access Type: Read-only 31 30 – – – – – – – – • WDUNF: Watchdog Underflow 0: No Watchdog underflow occurred since the ...
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Shutdown Controller (SHDWC) 18.1 Overview The Shutdown Controller controls the power supplies VDDIO and VDDCORE and the wake-up detection on debounced input lines. 18.2 Block Diagram Figure 18-1. Shutdown Controller Block Diagram Shutdown Controller SHDW_MR CPTWK0 WKMODE0 WKUP0 RTTWKEN ...
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Product Dependencies 18.4.1 Power Management The Shutdown Controller is continuously clocked by Slow Clock. The Power Management Con- troller has no effect on the behavior of the Shutdown Controller. 18.5 Functional Description The Shutdown Controller manages the main power ...
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Shutdown Controller (SHDWC) User Interface Table 18-2. Register Mapping Offset Register 0x00 Shutdown Control Register 0x04 Shutdown Mode Register 0x08 Shutdown Status Register 6249H–ATARM–27-Jul-09 Name Access SHDW_CR Write-only SHDW_MR Read-write SHDW_SR Read-only AT91SAM9263 Reset - 0x0000_0103 0x0000_0000 145 ...
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Shutdown Control Register Register Name: SHDW_CR Address: 0xFFFFFD10 Access Type: Write-only – – – – – – • SHDW: Shutdown Command effect KEY is correct, ...
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Shutdown Mode Register Register Name: SHDW_MR Address: 0xFFFFFD14 Access Type: Read/Write 31 30 – – – – – CPTWK0 • WKMODE0: Wake-up Mode 0 WKMODE[1: ...
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Shutdown Status Register Register Name: SHDW_SR Address: 0xFFFFFD18 Access Type: Read-only 31 30 – – – – – – – – • WAKEUP0: Wake-up 0 Status wake-up event occurred on ...
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General Purpose Backup Registers (GPBR) 19.1 Overview The System Controller embeds 20 general-purpose backup registers. 19.2 General Purpose Backup Registers (GPBR) User Interface Table 19-1. Register Mapping Offset Register 0x0 General Purpose Backup Register 0 ... ... 0x4C General ...
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General Purpose Backup Register x Register Name:SYS_GPBRx Addresses: 0xFFFFFD60 [0], 0xFFFFFD64 [1], 0xFFFFFD68 [2], 0xFFFFFD6C [3], 0xFFFFFD70 [4], 0xFFFFFD74 [5], 0xFFFFFD78 [6], 0xFFFFFD7C [7], 0xFFFFFD80 [8], 0xFFFFFD84 [9], 0xFFFFFD88 [10], 0xFFFFFD8C [11], 0xFFFFFD90 [12], 0xFFFFFD94 [13], 0xFFFFFD98 [14], 0xFFFFFD9C ...
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AT91SAM9263 Bus Matrix 20.1 Description Bus Matrix implements a multi-layer AHB, based on AHB-Lite protocol, that enables parallel access paths between multiple AHB masters and slaves in a system, which increases the over- all bandwidth. Bus Matrix interconnects 9 ...
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FIXED_DEFMSTR field allows to choose a fixed default master provided that DEFMSTR_TYPE is set to fixed default master. Please refer to the Bus Matrix user interface description. 20.4 Arbitration The Bus Matrix provides an arbitration mechanism that allows to reduce ...
Page 153
This selection can be done through the field ULBT of the Master Configuration Registers (MATRIX_MCFG). 20.4.1.2 Slot Cycle Limit Arbitration The Bus Matrix contains specific logic to break too long accesses such as very long bursts on a very slow ...
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For each slave, the priority of each master may be defined through the Priority Registers for Slaves (MATRIX_PRAS ...
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Bus Matrix (MATRIX) User Interface Table 20-1. Register Mapping Offset Register 0x0000 Master Configuration Register 0 0x0004 Master Configuration Register 1 0x0008 Master Configuration Register 2 0x000C Master Configuration Register 3 0x0010 Master Configuration Register 4 0x0014 Master Configuration ...
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Address: 0xFFFFEC00 Access Type:Read-write 31 30 – – – – – – – – • ULBT: Undefined Length Burst Type 0: Infinite Length Burst No predicted end of burst is generated and therefore INCR ...
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Bus Matrix Slave Configuration Registers Register Name:MATRIX_SCFG0...MATRIX_SCFG6 Address: 0xFFFFEC40 Access Type:Read-write 31 30 – – – – – • SLOT_CYCLE: Maximum Number of Allowed Cycles for a Burst When the SLOT_CYCLE limit is ...
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Bus Matrix Priority Registers A For Slaves Register Name:MATRIX_PRAS0...MATRIX_PRAS6 Addresses: 0xFFFFEC80 [0], 0xFFFFEC88 [1], 0xFFFFEC90 [2], 0xFFFFEC98 [3], 0xFFFFECA0 [4], 0xFFFFECA8 [5], 0xFFFFECB0 [6] Access Type:Write-only 31 30 – – – – – – 7 ...
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Bus Matrix Master Remap Control Register Register Name:MATRIX_MRCR Address: 0xFFFFED00 Access Type:Read-write Reset: 0x0000_0000 31 30 – – – – – – RCB7 RCB6 • RCBx: Remap Command Bit for AHB Master x ...
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Chip Configuration User Interface Table 20-2. Chip Configuration User Interface Offset Register 0x0110 Reserved 0x0114 Bus Matrix TCM Configuration Register 0x0118 - 0x011C Reserved 0x0120 EBI0 Chip Select Assignment Register 0x0124 EBI1 Chip Select Assignment Register 0x0128 - 0x01FC ...
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EBI0 Chip Select Assignment Register Register Name:EBI0_CSA Access Type:Read-write Reset: 0x0001_0000 31 30 – – – – – – – – EBI0_CS5A • EBI0_CS1A: EBI0 Chip Select 1 Assignment 0 = EBI0 Chip ...
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EBI1 Chip Select Assignment Register Register Name:EBI1_CSA Access Type:Read-write Reset: 0x0001_0000 31 30 – – – – – – – – • EBI1_CS1A: EBI1 Chip Select 1 Assignment 0 = EBI1 Chip Select ...
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External Bus Interface (EBI) 21.1 Overview The External Bus Interface (EBI) is designed to ensure the successful data transfer between several external devices and the embedded Memory Controller of an ARM-based device. The Static Memory, SDRAM and ECC Controllers ...
Page 164
Block Diagram 21.2.1 External Bus Interface 0 Figure 21-1 Figure 21-1. Organization of the External Bus Interface 0 Bus Matrix AHB Address Decoders AT91SAM9263 164 shows the organization of the External Bus Interface 0. External Bus Interface 0 SDRAM ...
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External Bus Interface 1 Figure 21-2 Figure 21-2. Organization of the External Bus Interface 1 Bus Matrix AHB Address Decoders 6249H–ATARM–27-Jul-09 shows the organization of the External Bus Interface 1. External Bus Interface 1 SDRAM Controller Static Memory Controller ...
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I/O Lines Description Table 21-1. EBI0 I/O Lines Description Name Function EBI0_D0 - EBI0_D31 Data Bus EBI0_A0 - EBI0_A25 Address Bus EBI0_NWAIT External Wait Signal EBI0_NCS0 - EBI0_NCS5 Chip Select Lines EBI0_NWR0 - EBI0_NWR3 Write Signals EBI0_NRD Read Signal ...
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Table 21-2. EBI1 I/O Lines Description Name Function EBI1_D0 - EBI1_D31 Data Bus EBI1_A0 - EBI1_A22 Address Bus EBI1_NWAIT External Wait Signal EBI1_NCS0 - EBI1_NCS2 Chip Select Lines EBI1_NWR0 - EBI1_NWR3 Write Signals EBI1_NRD Read Signal EBI1_NWE Write Enable EBI1_NBS0 ...
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Table 21-3. EBIx_NWR1/NBS1/CFIOR EBIx_A0/NBS0 EBIx_A1/NBS2/NWR2 EBIx_A[11:2] EBIx_SDA10 EBIx_A12 EBIx_A[14:13] EBIx_A[22:15] EBIx_A[25:23] EBIx_D[31:0] Notes: 6249H–ATARM–27-Jul-09 EBIx Pins and Memory Controllers I/O Lines Connections (1) EBIx Pins ( indicates Only for EBI0 AT91SAM9263 SDRAMC I/O Lines ...
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Hardware Interface Table 21-4 for each Memory Controller. Table 21-4. EBI Pins and External Static Devices Connections 8-bit Static Signals: Device EBI0_, EBI1_ Controller D15 – D16 - D23 – D24 ...
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Table 21-5. EBI Pins and External Devices Connections Signals: EBI0_, EBI1_ Controller D15 D16 - D31 A0/NBS0 A1/NWR2/NBS2 A2 - A10 A11 SDA10 A12 A13 - A14 A15 A16/BA0 A17/BA1 A18 - A20 A21/NANDALE A22/NANDCLE ...
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Table 21-5. EBI Pins and External Devices Connections (Continued) Signals: EBI0_, EBI1_ Controller SDCK SDCKE RAS CAS SDWE (7) NWAIT (2) Pxx (2) Pxx (2) Pxx Notes: 1. Not directly connected to the CompactFlash slot. Permits the control of the ...
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Connection Examples Figure 21-3 Figure 21-3. EBI Connections to Memory Devices EBI D0-D31 RAS CAS SDCK SDCKE SDWE A0/NBS0 NWR1/NBS1 A1/NWR2/NBS2 NWR3/NBS3 NRD/NOE NWR0/NWE SDA10 A2-A15 A16/BA0 A17/BA1 A18-A25 NCS0 NCS1/SDCS NCS2 NCS3 NCS4 NCS5 6249H–ATARM–27-Jul-09 shows an example ...
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Product Dependencies 21.4.1 I/O Lines The pins used for interfacing the External Bus Interface may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the External Bus Interface pins to their peripheral ...
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CompactFlash Support (EBI0 only) The External Bus Interface 0 integrates circuitry that interfaces to CompactFlash devices. The CompactFlash logic is driven by the Static Memory Controller (SMC) on the NCS4 and/or NCS5 address space. Programming the EBI0_CS4A and/or EBI0_CS5A ...
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Table 21-6. A[23:21] 000 010 100 110 111 21.5.6.2 CFCE1 and CFCE2 Signals To cover all types of access, the SMC must be alternatively set to drive 8-bit data bus or 16-bit data bus. The odd byte access on the ...
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Read/Write Signals In I/O mode and True IDE mode, the CompactFlash logic drives the read and write command signals of the SMC on CFIOR and CFIOW signals, while the CFOE and CFWE signals are deac- tivated. Likewise, in common ...
Page 177
Multiplexing of CompactFlash Signals on EBI Pins Table 21-9 on page 177 Flash logic signals with other EBI signals on the EBI pins. The EBI pins in dedicated to the CompactFlash interface as soon as the EBI0_CS4A and/or EBI0_CS5A ...
Page 178
Application Example Figure 21-6 on page 178 CFRNW signals are not directly connected to the CompactFlash slot 0, but do control the direc- tion and the output enable of the buffers between the EBI and the CompactFlash Device. The ...
Page 179
NAND Flash Support External Bus Interfaces 0 and 1 integrate circuitry that interfaces to NAND Flash devices. 21.5.7.1 External Bus Interface 0 The NAND Flash logic is driven by the Static Memory Controller on the NCS3 address space. Programming ...
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NAND Flash Signals The address latch enable and command latch enable signals on the NAND Flash device are driven by address bits A22 and A21 of the EBI address bus. The command, address or data words on the data ...
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Implementation Examples The following hardware configurations are given for illustration only. The user should refer to the memory manufacturer web site to check current device availability. 21.6.1 16-bit SDRAM Figure 21-9. Hardware Configuration 21.6.1.1 Software Configuration The following configuration ...
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SDRAM 21.6.2.1 Hardware Configuration D[0..31] A[0..14] (Not used A12 A10 A11 SDA10 SDA10 A13 BA0 BA0 BA1 BA1 A14 SDCKE SDCKE SDCK SDCK 1%6 A0 1%6 CFIOR_NBS1_NWR1 CAS CAS RAS ...
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NAND Flash 21.6.3.1 Hardware Configuration D[0..7] CLE ALE NANDOE NANDWE (ANY PIO) (ANY PIO) 21.6.3.2 Software Configuration The following configuration has to be performed: • Assign the EBI CS3 to the NAND Flash by setting the bit EBI_CS3A ...
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NAND Flash 21.6.4.1 Hardware Configuration D[0..15] CLE ALE NANDOE NANDWE (ANY PIO) (ANY PIO) 21.6.4.2 Software Configuration The software configuration is the same as for an 8-bit NAND Flash except the data bus width programmed in the mode ...
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NOR Flash on NCS0 21.6.5.1 Hardware Configuration D[0..15] A[1..22] NRST NWE NCS0 NRD 21.6.5.2 Software Configuration The default configuration for the Static Memory Controller, byte select mode, 16-bit data bus, Read/Write controlled by Chip Select, allows boot on 16-bit ...
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Compact Flash 21.6.6.1 Hardware Configuration D[0..15] D15 D14 D13 D12 D11 D10 A25/CFRNW 4 CFCSx (CFCS0 or CFCS1) 5 (ANY PIO) &$5' '(7(&7 A[0..10] A10 ...
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Software Configuration The following configuration has to be performed: • Assign the EBI CS4 and/or EBI_CS5 to the CompactFlash Slot 0 or/and Slot 1 by setting the bit EBI_CS4A or/and EBI_CS5A in the EBI Chip Select Assignment Register located ...
Page 188
Compact Flash True IDE 21.6.7.1 Hardware Configuration D[0..15] D15 D14 D13 D12 D11 D10 A25/CFRNW 4 CFCSx (CFCS0 or CFCS1) 5 (ANY PIO) &$5' '(7(&7 A[0..10] A10 A9 A8 ...
Page 189
Software Configuration The following configuration has to be performed: • Assign the EBI CS4 and/or EBI_CS5 to the CompactFlash Slot 0 or/and Slot 1 by setting the bit EBI_CS4A or/and EBI_CS5A in the EBI Chip Select Assignment Register located ...
Page 190
AT91SAM9263 190 6249H–ATARM–27-Jul-09 ...
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Static Memory Controller (SMC) 22.1 Overview The Static Memory Controller (SMC) generates the signals that control the access to the exter- nal memory devices or peripheral devices. It has 8 Chip Selects and a 26-bit address bus. The 32-bit ...
Page 192
Application Example 22.4.1 Hardware Interface Figure 22-1. SMC Connections to Static Memory Devices D0-D31 A0/NBS0 NWR0/NWE NWR1/NBS1 A1/NWR2/NBS2 NWR3/NBS3 NCS0 NCS1 NCS2 NCS3 NCS4 NCS5 NCS6 NCS7 A2 - A25 Static Memory Controller AT91SAM9263 192 128K x 8 SRAM ...
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Product Dependencies 22.5.1 I/O Lines The pins used for interfacing the Static Memory Controller may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the Static Memory Con- troller pins to their ...
Page 194
Connection to External Devices 22.7.1 Data Bus Width A data bus width bits can be selected for each chip select. This option is con- trolled by the field DBW in SMC_MODE (Mode Register) for ...
Page 195
Figure 22-5. Memory Connection for a 32-bit Data Bus 22.7.2.1 Byte Write Access Byte write access supports one byte write signal per byte of the data bus and a single read signal. Note that the SMC does not allow boot ...
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Figure 22-6. 22.7.2.3 Signal Multiplexing Depending on the BAT, only the write signals or the byte select signals are used. To save IOs at the external bus interface, control signals at the SMC interface are multiplexed. shows signal multiplexing depending ...
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Figure 22-7. Connection of 2x16-bit Data Bus on a 32-bit Data Bus (Byte Select Option) Table 22-3. SMC Multiplexed Signal Translation Signal Name Device Type 1x32-bit Byte Access Type (BAT) Byte Select NBS0_A0 NBS0 NWE_NWR0 NWE NBS1_NWR1 NBS1 NBS2_NWR2_A1 NBS2 ...
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Standard Read and Write Protocols In the following sections, the byte access type is not considered. Byte select lines (NBS0 to NBS3) always have the same timing as the A address bus. NWE represents either the NWE sig- nal ...
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NCS Waveform Similarly, the NCS signal can be divided into a setup time, pulse length and hold time: 1. NCS_RD_SETUP: the NCS setup time is defined as the setup time of address before the NCS falling edge. 2. NCS_RD_PULSE: ...
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Figure 22-9. No Setup, No Hold On NRD and NCS Read Signals NBS0,NBS1, NBS2,NBS3, A0, A1 22.8.1.5 Null Pulse Programming null pulse is not permitted. Pulse must be at least set null value leads to unpredictable behavior. ...