AT91SAM9263B-CU Atmel, AT91SAM9263B-CU Datasheet - Page 292

• Manufacturer Part Number: AT91SAM9263B-CU
• Description: IC ARM9 MCU 200 MHZ 324-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9263B-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 240MHz
• Connectivity: CAN, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: 2-Wire, EBI, I2S, MCI, SPI, USART
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9263-EK
• Minimum Operating Temperature: - 40 C
• Package: 324TFBGA
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 200 MHz
• Operating Supply Voltage: 1.8|2.5|3.3 V
• Controller Family/series: AT91SAM9xxx
• No. Of I/o's: 160
• Ram Memory Size: 96KB
• Cpu Speed: 240MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• For Use With: AT91SAM9263-EK - KIT EVAL FOR AT91SAM9263AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q3735625

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AT91SAM9263
4. After the DMAC channel has been programmed, enable the channel by writing a ‘1’ to
5. Source and destination request single and burst DMAC transactions to transfer the
6. When the block transfer has completed, the DMAC reloads the DMAC_SARx register.
7. The DMA transfer proceeds as follows:
a. Write the starting source address in the DMAC_SARx register for channel x.
b. Write the starting destination address in the DMAC_DARx register for channel x.
c. Program DMAC_CTLx and DMAC_CFGx according to Row 3 as shown in
d. Write the control information for the DMA transfer in the DMAC_CTLx register for
– i. Set up the transfer type (memory or non-memory peripheral for source and
– ii. Set up the transfer characteristics, such as:
e. If gather is enabled (DMAC_CTLx.S_GATH_EN is enabled), program the
f.
g. Write the channel configuration information into the DMAC_CFGx register for chan-
– i. Designate the handshaking interface type (hardware or software) for the source
– ii. If the hardware handshaking interface is activated for the source or destination
the DMAC_ChEnReg.CH_EN bit. Make sure that bit 0 of the DMAC_DmaCfgReg regis-
ter is enabled.
block of data (assuming non-memory peripherals). The DMAC acknowledges at the
completion of every transaction (burst and single) in the block and carries out the block
transfer.
The DMAC_DARx register remains unchanged. Hardware sets the block complete
interrupt. The DMAC then samples the row number as shown in
277. If the DMAC is in Row 1, then the DMA transfer has completed. Hardware sets the
transfer complete interrupt and disables the channel. So you can either respond to the
Block Complete or Transfer Complete interrupts, or poll for the Channel Enable
(DMAC_ChEnReg.CH_EN) bit until it is cleared by hardware, to detect when the trans-
fer is complete. If the DMAC is not in Row 1, the next step is performed.
destination) and flow control device by programming the TT_FC of the DMAC_CTLx
register.
and destination peripherals. This is not required for memory. This step requires
programming the HS_SEL_SRC/HS_SEL_DST bits, respectively. Writing a ‘0’
activates the hardware handshaking interface to handle source/destination requests
for the specific channel. Writing a ‘1’ activates the software handshaking interface to
handle source/destination requests.
peripheral, assign handshaking interface to the source and destination peripheral.
This requires programming the SRC_PER and DEST_PER bits, respectively.
– Transfer width for the source in the SRC_TR_WIDTH field.
– Transfer width for the destination in the DST_TR_WIDTH field.
– Source master layer in the SMS field where source resides.
– Destination master layer in the DMS field where destination resides.
– Incrementing/decrementing or fixed address for source in SINC field.
– Incrementing/decrementing or fixed address for destination in DINC field.
25-2 on page
channel x. For example, in this register, you can program the following:
DMAC_SGRx register for channel x.
If scatter is enabled (DMAC_CTLx.D_SCAT_EN), program the DMAC_DSRx regis-
ter for channel x.
nel x.
277. Program the DMAC_LLPx register with ‘0’.
Table 25-2 on page
6249H–ATARM–27-Jul-09
Table