AT91SAM9263B-CU Atmel, AT91SAM9263B-CU Datasheet - Page 269

• Manufacturer Part Number: AT91SAM9263B-CU
• Description: IC ARM9 MCU 200 MHZ 324-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9263B-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 240MHz
• Connectivity: CAN, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: 2-Wire, EBI, I2S, MCI, SPI, USART
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9263-EK
• Minimum Operating Temperature: - 40 C
• Package: 324TFBGA
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 200 MHz
• Operating Supply Voltage: 1.8|2.5|3.3 V
• Controller Family/series: AT91SAM9xxx
• No. Of I/o's: 160
• Ram Memory Size: 96KB
• Cpu Speed: 240MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• For Use With: AT91SAM9263-EK - KIT EVAL FOR AT91SAM9263AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q3735625

25. DMA Controller (DMAC)
25.1
25.2
25.3
25.3.1
6249H–ATARM–27-Jul-09
Overview
Block Diagram
Functional Description
Basic Definitions
The DMA Controller (DMAC) is an AHB-central DMA controller core that transfers data from a
source peripheral to a destination peripheral over one or more AMBA buses. One channel is
required for each source/destination pair. In the most basic configuration, the DMAC has one
master interface and one channel. The master interface reads the data from a source and writes
it to a destination. Two AMBA transfers are required for each DMA data transfer. This is also
known as a dual-access transfer.
The DMAC is programmed via the AHB slave interface.
Figure 25-1. DMA Controller (DMAC) Block Diagram
Source peripheral: Device on an AMBA layer from where the DMAC reads data, which is then
stored in the channel FIFO. The source peripheral teams up with a destination peripheral to form
a channel.
Destination peripheral: Device to which the DMAC writes the stored data from the FIFO (previ-
ously read from the source peripheral).
Memory: Source or destination that is always “ready” for a DMA transfer and does not require a
handshaking interface to interact with the DMAC. A peripheral should be assigned as memory
DMARQ0..3
AHB Master
AHB Slave
AHB Master
Handshaking
AHB Slave
Interface
Interface
Hardware
Interface
DMA Controller
SRC
FSM
Channel 0
CFG
FIFO
Channel 1
FSM
DST
AT91SAM9263
Generator
Interrupt
irq_dma
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