sed1355 ETC-unknow, sed1355 Datasheet - Page 97

• Manufacturer Part Number: sed1355
• Description: Sed1355 Embedded Ramdac Lcd/crt Controller
• Manufacturer: ETC-unknow

Epson Research and Development
Vancouver Design Center
7.5.8 8-Bit Dual Color Passive LCD Panel Timing
VDP
VNDP
HDP
HNDP
Hardware Functional Specification
Issue Date: 99/05/18
UD[3:0], LD[3:0]
FPDAT7 (UD3)
FPDAT6 (UD2)
FPDAT5 (UD1)
FPDAT4 (UD0)
FPDAT2 (UD2)
FPDAT1 (UD1)
FPDAT0 (UD0)
FPDAT3 (LD3)
* Diagram drawn with 2 FPLINE vertical blank period
Example timing for a 640x480 panel
= Vertical Display Period
= Vertical Non-Display Period
= Horizontal Display Period
= Horizontal Non-Display Period
FPFRAME
FPSHIFT
FPLINE
FPLINE
MOD
MOD
Figure 7-38: 8-Bit Dual Color Passive LCD Panel Timing
241-G1
241-R 1
241-B1
241-R 2
1-R1
1-R2
1-B1
1-G1
LINE 1/241
241-G2
24 1-B2
241-R3
241-G3
1-R 3
1-G3
1-G2
1-B2
LINE 2/242
241-B 3
241-R 4
241-G4
241-B4
1-B3
1-R4
1-G4
1-B4
= (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1
= (REG[0Ah] bits [5:0]) + 1
= ((REG[04h] bits [6:0]) + 1)*8Ts
= ((REG[05h] bits [4:0]) + 1)*8Ts
241-G5
241-B5
241-R 6
241-R5
1-G5
1-R 5
1-B 5
1-R6
LINE 3/243
241-G6
241-B6
241-R7
241-G7
1-G6
1-B6
1-R7
1-G7
LINE 4/244
VDP
241-R8
241-G8
241-B8
241-B7
1-R8
1-B7
1-G8
1-B8
HDP
LINE 239/479 LINE 240/480
VNDP
1-G640
1-B639
1-R640
1-B640
G640
B639
R640
2 41-
241-
B640
241-
2 41-
HNDP
LINE 1/241
LINE 2/242
X23A-A-001-11
SED1355
Page 91