sed1355 ETC-unknow, sed1355 Datasheet - Page 152

• Manufacturer Part Number: sed1355
• Description: Sed1355 Embedded Ramdac Lcd/crt Controller
• Manufacturer: ETC-unknow

Page 146
SED1355
X23A-A-001-11
MCLK = 40MHz
MCLK = 33MHz
(Speed Grade)
DRAM Type
EDO-DRAM
EDO-DRAM
50ns
60ns
1
• CRT.
• Simultaneous CRT + Single Panel.
• Simultaneous CRT + Dual
• Single Panel.
• Dual Monochrome/Color Panel with Half
• Dual Monochrome Panel with Half Frame
• Simultaneous CRT + Dual Mono Panel
• Dual Color Panel with Half Frame Buffer
• CRT.
• Simultaneous CRT + Single Panel.
• Simultaneous CRT + Dual
• Single Panel.
• Dual Monochrome/Color Panel with Half
• Dual Monochrome Panel with Half Frame
• Simultaneous CRT + Dual Monochrome
• Dual Color Panel with Half Frame Buffer
Monochrome/Color Panel with Half
Frame Buffer Disabled.
Frame Buffer Disabled.
Buffer Enabled.
with Half Frame Buffer Enable.
Enabled.
Monochrome/Color Panel with Half
Frame Buffer Disabled.
Frame Buffer Disabled.
Buffer Enabled.
Panel with Half Frame Buffer Enable.
Enabled.
Table 14-6: Theoretical Maximum Bandwidth M byte/sec, Cursor/Ink disabled
640x480 Display
Max. Pixel
Clock
(MHz)
13.3
13.3
16.5
16.5
16.5
40
40
20
40
20
40
20
33
33
33
11
33
11
1 bpp
6.67
6.67
6.67
6.27
6.67
6.67
6.36
6.67
6.67
5.17
5.24
5.5
5.5
5.5
5.5
5.5
5.5
5.5
Maximum Bandwidth (M byte/sec)
2 bpp
6.67
6.67
6.67
5.11
6.67
6.67
5.44
6.67
6.67
4.21
4.49
5.5
5.5
5.5
5.5
5.5
5.5
5.5
Epson Research and Development
Hardware Functional Specification
4 bpp
6.67
6.60
6.67
6.67
6.67
6.27
6.67
5.5
5.5
5.5
5.5
5.5
5.5
5.5
-
-
-
-
Vancouver Design Center
Issue Date: 99/05/18
8 bpp
6.36
6.27
6.67
6.67
6.67
6.27
6.67
5.24
5.17
5.17
5.5
5.5
5.5
5.5
-
-
-
-
16 bpp
1.79
0.41
6.67
3.94
6.67
6.67
1.47
0.34
3.25
5.5
5.5
5.5
-
-
-
-
-
-