sed1355 ETC-unknow, sed1355 Datasheet - Page 121

• Manufacturer Part Number: sed1355
• Description: Sed1355 Embedded Ramdac Lcd/crt Controller
• Manufacturer: ETC-unknow

Epson Research and Development
Vancouver Design Center
bit 3
bit 2
bit 1
bit 7
bit 7
Hardware Functional Specification
Issue Date: 99/05/18
General IO Pins Control Register 0
REG[20h]
n/a
General IO Pins Control Register 1
REG[21h]
GPO Control
Performance Enhancement Register 0
REG[22h]
Reserved
n/a
n/a
RC Timing
Value Bit 1
Note
GPIO3 Pin IO Status
When GPIO3 is configured as an output (see REG[1Eh]), a “1” in this bit drives GPIO3 high and a
“0” in this bit drives GPIO3 low.
When GPIO3 is configured as an input, a read from this bit returns the status of GPIO3.
GPIO2 Pin IO Status
When GPIO2 is configured as an output (see REG[1Eh]), a “1” in this bit drives GPIO2 high and a
“0” in this bit drives GPIO2 low.
When GPIO2 is configured as an input, a read from this bit returns the status of GPIO2.
GPIO1 Pin IO Status
When GPIO1 is configured as an output (see REG[1Eh]), a “1” in this bit drives GPIO1 high and a
“0” in this bit drives GPIO1 low.
When GPIO1 is configured as an input, a read from this bit returns the status of GPIO1.
GPO Control
This bit is used to control the state of the SUSPEND# pin when it is configured as General Purpose
Output (GPO). When this bit = 0, the GPO output is set to the reset state. When this bit = 1, the
GPO output is set to the inverse of the reset state. For information on the reset state of this pin see
“Miscellaneous Interface Pin Descriptions“ on page 32 and “Summary of Power On/Reset
Options“ on page 33.
Reserved
Changing this register to non-zero value, or to a different non-zero value, should be done only
when there are no read/write DRAM cycles. This condition occurs when all of the following are
true: the Display FIFO is disabled (REG[23h] bit 7 = 1), and the Half Frame Buffer is disabled
(REG[1Bh] bit 0 = 1), and the Ink/Cursor is inactive (Reg[27h] bits 7-6 = 00). This condition also
occurs when the CRT and LCD enable bits (Reg[0Dh] bits 1-0) have remained 0 since chip reset.
For further programming information, see SED1355 Programming Notes and Examples, docu-
ment number X23A-G-003-xx.
n/a
n/a
RC Timing
Value Bit 0
n/a
n/a
RAS#-to-
CAS# Delay
Value
GPIO3 Pin
IO Status
n/a
RAS#
Precharge
Timing Value
Bit 1
GPIO2 Pin
IO Status
n/a
RAS#
Precharge
Timing Value
Bit 0
n/a
GPIO1 Pin
IO Status
Reserved
n/a
n/a
Reserved
X23A-A-001-11
SED1355
Page 115
RW
RW
RW