sed1355 ETC-unknow, sed1355 Datasheet - Page 84

• Manufacturer Part Number: sed1355
• Description: Sed1355 Embedded Ramdac Lcd/crt Controller
• Manufacturer: ETC-unknow

Page 78
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SED1355
X23A-A-001-11
Symbol
Ts
t1
t4
t5
t6
t9
t10
t11
t12
t13
t14
t1
t2
t3
t4
t5
t6
t7
t8
t9
min
min
min
min
min
Data Timing
Sync Timing
= pixel clock period = memory clock, [memory clock]/2, [memory clock]/3, [memory clock]/4 (see REG[19h] bits [1:0])
= t4
= [((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0]) + 1)*8] Ts
= [(((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0]) + 1)*8)-1] Ts
= [((REG[05h] bits [4:0]) + 1)*8 - 27] Ts
= [((REG[05h] bits [4:0]) + 1)*8 - 18] Ts
min
FPFRAME setup to FPLINE pulse trailing edge
FPFRAME hold from FPLINE pulse trailing edge
FPLINE pulse width
FPLINE period
MOD delay from FPLINE pulse trailing edge
FPSHIFT falling edge to FPLINE pulse leading edge
FPLINE pulse trailing edge to FPSHIFT falling edge
FPSHIFT period
FPSHIFT falling edge to FPLINE pulse trailing edge
FPLINE pulse trailing edge to FPSHIFT rising edge
FPSHIFT pulse width high
FPSHIFT pulse width low
UD[3:0] setup to FPSHIFT falling edge
UD[3:0] hold to FPSHIFT falling edge
- 14Ts
FPFRAME
Figure 7-25: 4-Bit Single Monochrome Passive LCD Panel A.C. Timing
FPSHIFT
Table 7-23: 4-Bit Single Monochrome Passive LCD Panel A.C. Timing
FPLINE
FPLINE
UD[3:0]
MOD
Parameter
t6
t5
t9
t1
t10
t3
t7
t10 + t11
t2
t13
note 2
note 3
note 4
note 5
note 6
Min
14
20
9
4
2
2
2
2
1
t4
t14
Epson Research and Development
t11
Hardware Functional Specification
Typ
2
t8
t12
Vancouver Design Center
Max
Issue Date: 99/05/18
Ts (note 1)
Units
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts