sed1355 ETC-unknow, sed1355 Datasheet - Page 148

• Manufacturer Part Number: sed1355
• Description: Sed1355 Embedded Ramdac Lcd/crt Controller
• Manufacturer: ETC-unknow

Page 142
14.2 Frame Rate Calculation
(Speed Grade)
SED1355
X23A-A-001-11
MClk = 40MHz
DRAM Type
EDO-DRAM
N
N
N
50ns
RP
RCD
RC
= 1.5
= 4
= 2
1
• Single Panel.
• CRT.
• Dual Monochrome/Color Panel
• Simultaneous CRT + Single Panel.
• Simultaneous CRT + Dual
• Dual Color with Half Frame Buffer
• Dual Mono with Half Frame Buffer
with Half Frame Buffer Disabled.
Monochrome/Color Panel with Half
Frame Buffer Disabled.
Enabled.
Enabled.
The frame rate is calculated using the following formula:
Where:
FrameRate
Display
VDP
VNDP
HDP
HNDP
Ts
Table 14-3: Example Frame Rates with Ink Disabled
=
5
---------------------------------------------------------------------------------------- -
HDP
= Vertical Display Period
= Vertical Non-Display Period
= Horizontal Display Period
= Horizontal Non-Display Period
= Pixel Clock
+
HNDP
5
PCLK
Resolution
800x600
800x600
640x480
640x240
480x320
320x240
640x480
max
VDP
2,3
2
+
VNDP
Color Depth
1/2/4/8
1/2/4/8
1/2/4/8
1/2/4/8
1/2/4/8
1/2/4/8
1/2/4/8
15/16
15/16
(bpp)
15/16
15/16
15/16
15/16
15/16
6
6
= in table below
= ((REG[04h] bits [6:0]) + 1) * 8Ts
= ((REG[05h] bits [4:0]) + 1) * 8Ts
= given in table below
= PCLK
= REG[09h] bits [1:0], REG[08h] bits [7:0] + 1
= REG[0Ah] bits [5:0] + 1
Maximum
Clock
(MHz)
Pixel
13.3
13.3
40
20
20
Epson Research and Development
HNDP(T
Minimum
Hardware Functional Specification
Panel
32
56
32
56
32
56
32
56
32
56
32
32
32
32
Vancouver Design Center
s
)
Issue Date: 99/05/18
Maximum Frame
Panel
123
119
247
242
243
232
471
441
123
80
78
80
53
82
Rate (Hz)
4
CRT
60
60
85
85
-
-
-
-
-
-
-
-
-
-