sed1355 ETC-unknow, sed1355 Datasheet - Page 428
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sed1355
Manufacturer Part Number
sed1355
Description
Sed1355 Embedded Ramdac Lcd/crt Controller
Manufacturer
ETC-unknow
Datasheet
1.SED1355.pdf
(509 pages)
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Page 12
4 VR4102/VR4111 to SED1355 Interface
4.1 Hardware Description
SED1355
X23A-G-007-05
NEC V
R
ADD[25:0]
DAT[15:0]
4102/V
LCDRDY
BUSCLK
LCDCS#
SHB#
WR#
Note:
When connecting the SED1355 RESET# pin, the system designer should be aware of all
conditions that may reset the SED1355 (e.g. CPU reset can be asserted during wake-up
from power-down modes, or during debug states).
RD#
Figure 4-1: NEC V
R
4111
Note
The NEC V
LCD controller. They provide the necessary internal address decoding and control signals.
The diagram below shows a typical implementation utilizing the SED1355.
For pin mapping see Table 3-1:, “Host Bus Interface Pin Mapping,” on page 10.
R
4102/V
R
4102/V
R
4111 Microprocessors are specifically designed to support an external
R
4111 to SED1355 Configuration Schematic
System RESET
ADD21
Pull-up
Interfacing to the NEC VR4102/VR4111™ Microprocessors
V
V
DD
DD
Epson Research and Development
WE0#
WE1#
RD#
CS#
WAIT#
M/R#
RESET#
AB[20:0]
DB[15:0]
BUSCLK
BS#
RD/WR#
SED1355
Vancouver Design Center
Issue Date: 99/05/05
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