sed1355 ETC-unknow, sed1355 Datasheet - Page 116

• Manufacturer Part Number: sed1355
• Description: Sed1355 Embedded Ramdac Lcd/crt Controller
• Manufacturer: ETC-unknow

Page 110
REG[13h] bits 7-0
REG[14h] bits 7-0
REG[15h] bits 3-0
REG[16h] bits 7-0
REG[17h] bits 2-0
SED1355
X23A-A-001-11
Screen 2 Display Start Address Register 0
REG[13h]
Start Address
Bit 7
Screen 2 Display Start Address Register 1
REG[14h]
Start Address
Bit 15
Screen 2 Display Start Address Register 2
REG[15h]
n/a
Memory Address Offset Register 0
REG[16h]
Memory
Address
Offset Bit 7
Memory Address Offset Register 1
REG[17h]
n/a
Start Address
Bit 6
Start Address
Bit 14
n/a
Memory
Address
Offset Bit 6
n/a
Screen 2 Start Address Bits [19:0]
These registers form the 20-bit address for the starting word of the Screen 2 image in
the display buffer.
Note that this is a word address.
A combination of this register and the Pixel Panning register (REG[18h]) can be used to uniquely
identify the start (top left) pixel within the Screen 2 image stored in the display buffer.
See “Display Configuration” for details.
Memory Address Offset Bits [10:0]
These bits form the 11-bit address offset from the starting word of line n to the starting word of line
n+1. This value is applied to both Screen 1 and Screen 2.
Note that this value is in words.
A virtual image can be formed by setting this register to a value greater than the width of the dis-
play. The displayed image is a window into the larger virtual image.
See “Section 10 Display Configuration” for details.
Start Address
Bit 5
Start Address
Bit 13
n/a
Memory
Address
Offset Bit 5
n/a
Start Address
Bit 4
Start Address
Bit 12
n/a
Memory
Address
Offset Bit 4
n/a
Start Address
Bit 3
Start Address
Bit 11
Start Address
Bit 19
Memory
Address
Offset Bit 3
n/a
Start Address
Bit 2
Start Address
Bit 10
Start Address
Bit 18
Memory
Address
Offset Bit 2
Memory
Address
Offset Bit 10
Epson Research and Development
Start Address
Bit 1
Start Address
Bit 9
Start Address
Bit 17
Memory
Address
Offset Bit 1
Memory
Address
Offset Bit 9
Hardware Functional Specification
Vancouver Design Center
Issue Date: 99/05/18
Start Address
Bit 0
Start Address
Bit 8
Start Address
Bit 16
Memory
Address
Offset Bit 0
Memory
Address
Offset Bit 8
RW
RW
RW
RW
RW