sed1355 ETC-unknow, sed1355 Datasheet - Page 77

• Manufacturer Part Number: sed1355
• Description: Sed1355 Embedded Ramdac Lcd/crt Controller
• Manufacturer: ETC-unknow

Epson Research and Development
Vancouver Design Center
Hardware Functional Specification
Issue Date: 99/05/18
Symbol
MD(write)
t1
t2
t3
t4
t5
t6
t7
t8
MD(read)
Memory
RAS#
CAS#
Clock
WE#
MA
Internal memory clock period
Random read cycle REG[22h] bit 6-5 == 00
Random read cycle REG[22h] bit 6-5 == 01
Random read cycle REG[22h] bit 6-5 == 10
RAS# precharge time (REG[22h] bits 3-2 = 00)
RAS# precharge time (REG[22h] bits 3-2 = 01)
RAS# precharge time (REG[22h] bits 3-2 = 10)
RAS# to CAS# delay time (REG[22h] bit 4 = 1 and
bits 3-2 = 00 or 10)
RAS# to CAS# delay time (REG[22h] bit 4 = 0 and
bits 3-2 = 00 or 10)
RAS# to CAS# delay time (REG[22h] bit 4 = 1 and
bits 3-2 = 01)
RAS# to CAS# delay time (REG[22h] bit 4 = 0 and
bits 3-2 = 01)
CAS# precharge time
CAS# pulse width
RAS# hold time
Row address setup time (REG[22h] bits 3-2 = 00)
Row address setup time (REG[22h] bits 3-2 = 01)
Row address setup time (REG[22h] bits 3-2 = 10)
t8
t3
t1
R
t12
Parameter
t9
Table 7-18: FPM-DRAM Read/Write/Read-Write Timing
t4
t10 t11
Figure 7-19: FPM-DRAM Read-Write Timing
C1
t5
d1
t6
t14
C2
d2
t1
t15
C3
d3
t21
1.45 t1 - 3
1.45 t1 - 3
2.45 t1 - 3
0.45 t1 - 3
0.45 t1 - 3
0.45 t1 - 3
1.45 t1 - 3
C1
2 t1 - 3
1 t1 - 3
2 t1 - 3
1 t1 - 3
1t1 - 3
2t1 - 3
t16
t18 t19
Min
5t1
4t1
3t1
40
d1
C2
d2
C3
d3
t17
t20
t7
Max
X23A-A-001-11
SED1355
Units
Page 71
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