sed1355 ETC-unknow, sed1355 Datasheet - Page 38

• Manufacturer Part Number: sed1355
• Description: Sed1355 Embedded Ramdac Lcd/crt Controller
• Manufacturer: ETC-unknow

Page 32
5.2.5 Miscellaneous
SED1355
X23A-A-001-11
SUSPEND# IO
CLKI
TESTEN
VDD
DACVDD
VSS
DACVSS
Pin Name
I
I
P
P
P
P
Type
71
69
70
12, 33, 55, 72,
97, 109
99, 102, 104
14, 32, 50, 68,
78, 87, 96, 110
98, 106
Pin #
CS/TS1
C
CD
P
P
P
P
Table 5-4: Miscellaneous Interface Pin Descriptions
Cell
Hi-Z if MD[9]=0
High if
MD[10:9]=01
Low if
MD[10:9]=11
Hi-Z
RESET# State
This pin can be used as a power-down input (SUSPEND#)
or as an output possibly used for controlling the LCD
backlight power:
• When MD9 = 0 at rising edge of RESET#, this pin is an
• When MD[10:9] = 01 at rising edge of RESET#, this pin
• When MD[10:9] = 11 at rising edge of RESET#, this pin
Input clock for the internal pixel clock (PCLK) and memory
clock (MCLK). PCLK and MCLK are derived from CLKI - see
REG[19h] for details.
Test Enable. This pin should be connected to V
operation.
V
DAC V
V
DAC V
DD
SS
active-low Schmitt input used to put the SED1355 into
Hardware Suspend mode - see Section 15, “Power Save
Modes” for details.
is an output (GPO) with a reset state of 1. The state of GPO
is controlled by REG[21h] bit 7.
is an output (GPO) with a reset state of 0. The state of GPO
is controlled by REG[21h] bit 7.
DD
SS
Description
Epson Research and Development
Hardware Functional Specification
Vancouver Design Center
Issue Date: 99/05/18
SS
for normal