sed1355 ETC-unknow, sed1355 Datasheet - Page 79

• Manufacturer Part Number: sed1355
• Description: Sed1355 Embedded Ramdac Lcd/crt Controller
• Manufacturer: ETC-unknow

Epson Research and Development
Vancouver Design Center
7.3.5 FPM-DRAM CAS Before RAS Refresh Timing
Hardware Functional Specification
Issue Date: 99/05/18
Symbol
t1
t2
t3
t4
t5
t6
Internal memory clock period
RAS# precharge time (REG[22h] bits 3-2 = 00)
RAS# precharge time (REG[22h] bits 3-2 = 01 or 10)
RAS# pulse width (REG[22h] bits 6-5 = 00 and bits 3-
2 = 00)
RAS# pulse width (REG[22h] bits 6-5 = 00 and bits 3-
2 = 01 or 10)
RAS# pulse width (REG[22h] bits 6-5 = 01 and bits 3-
2 = 00)
RAS# pulse width (REG[22h] bits 6-5 = 01 and bits 3-
2 = 01 or 10)
RAS# pulse width (REG[22h] bits 6-5 = 10 and bits 3-
2 = 00)
RAS# pulse width (REG[22h] bits 6-5 = 10 and bits 3-
2 = 01 or 10)
CAS# pulse width (REG[22h] bits 3-2 = 00)
CAS# pulse width (REG[22h] bits 3-2 = 01 or 10)
CAS# Setup to RAS#
CAS# Hold to RAS# (REG[22h] bits 6-5 = 00 and bits
3-2 = 00)
CAS# Hold to RAS# (REG[22h] bits 6-5 = 00 and bits
3-2 = 01 or 10)
CAS# Hold to RAS# (REG[22h] bits 6-5 = 01 and bits
3-2 = 00)
CAS# Hold to RAS# (REG[22h] bits 6-5 = 01 and bits
3-2 = 01 or 10)
CAS# Hold to RAS# (REG[22h] bits 6-5 = 10 and bits
3-2 = 00)
CAS# Hold to RAS# (REG[22h] bits 6-5 = 10 and bits
3-2 = 01 or 10)
Memory
Parameter
CAS#
Clock
RAS#
Figure 7-20: FPM-DRAM CAS Before RAS Refresh Timing
Table 7-19: FPM-DRAM CAS Before RAS Refresh Timing
t4
t2
t1
t5
t6
t3
2.45 t1 - 3
1.45 t1 - 3
2.45 t1 - 3
3.45 t1 - 3
1.45 t1 - 3
2.45 t1 - 3
0.45 t1 - 3
1.45 t1 - 3
0.45 t1 - 3
2.45 t1 - 3
3.45 t1 - 3
1.45 t1 - 3
2.45 t1 - 3
0.45 t1 - 3
1.45 t1 - 3
2 t1 - 3
1 t1 - 3
Min
40
Max
X23A-A-001-11
SED1355
Units
Page 73
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