sed1355 ETC-unknow, sed1355 Datasheet - Page 405

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sed1355

Manufacturer Part Number
sed1355
Description
Sed1355 Embedded Ramdac Lcd/crt Controller
Manufacturer
ETC-unknow
Datasheet

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Epson Research and Development
Vancouver Design Center
Interfacing to the PC Card Bus
Issue Date: 99/05/05
D[15:0]
A[25:0]
WAIT#
REG#
CE1#
CE2#
OE#
During a read cycle, OE# (output enable) is driven low. A write cycle is specified by
driving OE# high and driving the write enable signal (WE#) low. The cycle can be
lengthened by driving WAIT# low for the time needed to complete the cycle.
Figure 2-1: illustrates a typical memory access read cycle on the PC Card bus.
Transfer Start
Hi-Z
Figure 2-1: PC Card Read Cycle
ADDRESS VALID
DATA VALID
Transfer Complete
X23A-G-005-05
SED1355
Hi-Z
Page 9

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