sed1355 ETC-unknow, sed1355 Datasheet - Page 240

• Manufacturer Part Number: sed1355
• Description: Sed1355 Embedded Ramdac Lcd/crt Controller
• Manufacturer: ETC-unknow

Page 84
SED1355
X23A-G-003-05
**
**
**
**
**
**
**
** HNDP and VNDP must be calculated such that the desired frame rate
** is achieved.
*/
*(pRegs + 0x05) = 0x1F;
/*
** Register 6: HRTC/FPLINE Start Position - applicable to CRT/TFT only.
*/
*(pRegs + 0x06) = 0x00;
/*
** Register 7: HRTC/FPLINE Pulse Width - applicable to CRT/TFT only.
*/
*(pRegs + 0x07) = 0x00;
/*
** Registers 8-9: Vertical Display Height (VDP) - 480 lines.
**
*/
*(pRegs + 0x08) = 0xEF;
*(pRegs + 0x09) = 0x00;
/*
** Register A: Vertical Non-Display Period (VNDP)
**
**
**
*/
*(pRegs + 0x0A) = 0x01;
/*
** Register B: VRTC/FPFRAME Start Position - applicable to CRT/TFT only.
*/
*(pRegs + 0x0B) = 0x00;
/*
** Register C: VRTC/FPFRAME Pulse Width - applicable to CRT/TFT only.
*/
*(pRegs + 0x0C) = 0x00;
/*
** Register D: Display Mode - 8 BPP, LCD disabled.
*/
*(pRegs + 0x0D) = 0x0C;
/*
** Registers E-F: Screen 1 Line Compare - unless setting up for
**
*/
*(pRegs + 0x0E) = 0xFF;
Frame Rate = -----------------------------
This register must be programed with register 5 (HNDP)
to arrive at the frame rate closest to the desired
frame rate.
480/2 - 1 = 239t = 0xEF
split screen operation use 0x3FF.
= -----------------------------
(HDP + HNDP) * (VDP + VNDP)
(640 + HNDP) * (480 + VNDP)
16,500,000
/* 0001 1111 */
/* 0000 0000 */
/* 0000 0000 */
/* 1110 1111 */
/* 0000 0000 */
/* 0000 0001 */
/* 0000 0000 */
/* 0000 0000 */
/* 0000 1100 */
/* 1111 1111 */
Epson Research and Development
Programming Notes and Examples
Vancouver Design Center
Issue Date: 99/04/27