sed1355 ETC-unknow, sed1355 Datasheet - Page 56

no-image

sed1355

Manufacturer Part Number
sed1355
Description
Sed1355 Embedded Ramdac Lcd/crt Controller
Manufacturer
ETC-unknow
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
sed1355F0A
Manufacturer:
EPSON/爱普生
Quantity:
20 000
Part Number:
sed1355FOA
Manufacturer:
EPSON
Quantity:
996
Part Number:
sed1355FOA
Manufacturer:
EPSON/爱普生
Quantity:
20 000
Page 50
SED1355
X23A-A-001-11
Symbol
t11
t10
t12
t13
t7
t1
t2
t3
t4
t5
t6
t8
t9
1
2
Clock period
Clock pulse width high
Clock pulse width low
A[20:0], M/R# setup to first CLK where CS# = 0 and either -OE = 0 or -
WE = 0
A[20:0], M/R# hold from rising edge of either -OE or -WE
CS# hold from rising edge of either -OE or -WE
Falling edge of either -OE or -WE to -WAIT driven low
Rising edge of either -OE or -WE to -WAIT tri-state
D[15:0] setup to third CLK where CS# = 0 and -WE = 0 (write cycle)
D[15:0] hold (write cycle)
Falling edge -OE to D[15:0] driven (read cycle)
D[15:0] setup to rising edge -WAIT (read cycle)
Rising edge of -OE to D[15:0] tri-state (read cycle)
1.
2.
If the SED1355 host interface is disabled, the timing for -WAIT driven low is relative to the
falling edge of -OE, -WE or the first positive edge of CLK after A[20:0], M/R# becomes valid,
whichever one is later.
If the SED1355 host interface is disabled, the timing for D[15:0] driven is relative to the falling
edge of -OE or the first positive edge of CLK after A[20:0], M/R# becomes valid, whichever
one is later.
Parameter
Table 7-5: PC Card Timing
Min
20
10
10
6
6
0
0
0
5
0
0
0
5
3.0V
Epson Research and Development
Max
Hardware Functional Specification
15
25
25
Vancouver Design Center
Min
2.5
10
20
10
6
6
0
0
0
0
0
0
5
5.0V
Issue Date: 99/05/18
Max
10
10
10
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

Related parts for sed1355