sed1355 ETC-unknow, sed1355 Datasheet - Page 407

• Manufacturer Part Number: sed1355
• Description: Sed1355 Embedded Ramdac Lcd/crt Controller
• Manufacturer: ETC-unknow

Epson Research and Development
Vancouver Design Center
3 SED1355 Host Bus Interface
3.1 PC Card Host Bus Interface Pin Mapping
Interfacing to the PC Card Bus
Issue Date: 99/05/05
Note
Note
The SED1355 implements a 16-bit PC Card (PCMCIA) host bus interface which is used to
interface to the PC Card bus.
The PC Card host bus interface is selected by the SED1355 on the rising edge of RESET#.
After releasing reset the bus interface signals assume their selected configuration. For
details on SED1355 configuration, see Section 4.2, “SED1355 Hardware Configuration”
on page 15.
The following table shows the functions of each host bus interface signal.
At reset, the Host Interface Disable bit in the Miscellaneous Disable Register
(REG[1Bh] bit 7) is set to 1. This means that only REG[1Ah] (read-only) and
REG[1Bh] are accessible until a write to REG[1Bh] sets bit 7 to 0 making all regis-
ters accessible. When debugging a new hardware design, this can sometimes give the
appearance that the interface is not working, so it is important to remember to clear this
bit before proceeding with debugging.
1
2
the SED1355 PC Card host bus interface. For an example of how this can be accom-
plished see the discussion on BUSCLK in Section 3.2, “PC Card Host Bus Interface
Signals” on page 12.
Although a clock is not directly supplied by the PC Card interface, one is required by
The bus signal A0 is not used by the SED1355 internally.
Table 3-1: PC Card Host Bus Interface Pin Mapping
SED1355 Pin Name
BUSCLK
RD/WR#
AB[20:0]
DB[15:0]
RESET#
WAIT#
WE1#
WE0#
M/R#
RD#
CS#
BS#
PC Card (PCMCIA)
External Decode
External Decode
Inverted RESET
A[20:0]
D[15:0]
-WAIT
-CE2
-CE1
-WE
n/a
V
-OE
DD
2
1
X23A-G-005-05
SED1355
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