sed1355 ETC-unknow, sed1355 Datasheet - Page 52

• Manufacturer Part Number: sed1355
• Description: Sed1355 Embedded Ramdac Lcd/crt Controller
• Manufacturer: ETC-unknow

Page 46
SED1355
X23A-A-001-11
Symbol
t14
t10
t11
t12
t13
t15
t16
t17
t9
t1
t2
t3
t4
t5
t6
t7
t8
1
2
Clock period
Clock pulse width high
Clock pulse width low
A[20:1], M/R# setup to first CLK where CS# = 0 AS# = 0, and
either UDS#=0 or LDS# = 0
A[20:1], M/R# hold from AS#
CS# hold from AS#
R/W# setup to before to either UDS#=0 or LDS# = 0
R/W# hold from AS#
AS# = 0 and CS# = 0 to DTACK# driven high
AS# high to DTACK# high
First BCLK where AS# = 1 to DTACK# high impedance
D[15:0] valid to third CLK where CS# = 0 AS# = 0, and either
UDS#=0 or LDS# = 0 (write cycle)
D[15:0] hold from falling edge of DTACK# (write cycle)
Falling edge of UDS#=0 or LDS#=0 to D[15:0] driven (read
cycle)
D[15:0] valid to DTACK# falling edge (read cycle)
UDS# and LDS# high to D[15:0] invalid/high impedance (read
cycle)
AS# high setup to CLK
1.
2.
If the SED1355 host interface is disabled, the timing for DTACK# driven high is relative to the
falling edge of CS#, AS# or the first positive edge of CLK after A[20:1], M/R# becomes valid,
whichever one is later.
If the SED1355 host interface is disabled, the timing for D[15:0] driven is relative to the falling
edge of UDS#, LDS# or the first positive edge of CLK after A[20:1], M/R# becomes valid,
whichever one is later.
Parameter
Table 7-3: MC68000 Timing
Min
20
10
10
10
6
6
0
0
0
0
3
0
0
0
5
2
3.0V
Max
18
25
25
Epson Research and Development
Hardware Functional Specification
Min
2.5
20
10
10
10
6
6
0
0
0
0
3
0
0
0
2
Vancouver Design Center
5.0V
Issue Date: 99/05/18
Max
12
10
10
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns