sed1355 ETC-unknow, sed1355 Datasheet - Page 124

• Manufacturer Part Number: sed1355
• Description: Sed1355 Embedded Ramdac Lcd/crt Controller
• Manufacturer: ETC-unknow

Page 118
bit 7
bits 4-0
8.2.8 Look-Up Table Registers
SED1355
X23A-A-001-11
bit 6-5
Performance Enhancement Register 1
REG[23h]
Display FIFO
Disable
Look-Up Table Address Register
REG[24h]
LUT Address
Bit 7
CPU to
Memory Wait
State
Bit 1
LUT Address
Bit 6
Note
Note
Display FIFO Disable
When this bit = 1 the display FIFO is disabled and all data outputs are forced to zero (i.e., the
screen is blanked). This accelerates screen updates by allocating more memory bandwidth to CPU
accesses.
When this bit = 0 the display FIFO is enabled.
CPU to Memory Wait State Bits [1:0]
These bits are used to optimize the handshaking between the host interface and the memory con-
troller. The bits should be set according to the relationship between BCLK and MCLK – see the
table below where T
Display FIFO Threshold Bits [4:0]
These bits specify the display FIFO depth required to sustain uninterrupted display fetches. When
these bits are all “0”, the display FIFO depth is calculated automatically.
These bits should always be set to 0, except in the following configurations:
When in the above configurations, a value of 1Bh should be used.
Wait State Bits [1:0]
For further performance increase in dual panel mode disable the half frame buffer (see section
8.2.7) and disable the cursor (see section 8.2.9).
The utility 1355CFG will, given the correct configuration values, automatically generate the
correct values for the Performance Enhancement Registers.
CPU to
Memory Wait
State
Bit 0
LUT Address
Bit 5
Landscape mode at 15/16 bpp (with MCLK=PCLK),
Portrait mode at 8/16 bpp (with MCLK=PCLK).
00
01
10
11
Table 8-16: Minimum Memory Timing Selection
B
Display FIFO
Threshold
Bit 4
LUT Address
Bit 4
and T
M
are the BCLK and MCLK periods respectively.
Display FIFO
Threshold
Bit 3
LUT Address
Bit 3
no restrictions (default)
Display FIFO
Threshold
Bit 2
LUT Address
Bit 2
2T
Condition
undefined
undefined
M
- 4ns > T
Epson Research and Development
B
Display FIFO
Threshold
Bit 1
LUT Address
Bit 1
Hardware Functional Specification
Vancouver Design Center
Issue Date: 99/05/18
Display FIFO
Threshold
Bit 0
LUT Address
Bit 0
RW
RW