sed1355 ETC-unknow, sed1355 Datasheet - Page 429

• Manufacturer Part Number: sed1355
• Description: Sed1355 Embedded Ramdac Lcd/crt Controller
• Manufacturer: ETC-unknow

Epson Research and Development
Vancouver Design Center
4.2 SED1355 Hardware Configuration
4.3 NEC V
Interfacing to the NEC VR4102/VR4111™ Microprocessors
Issue Date: 99/05/05
MD0
MD[3:1]
MD4
MD5
MD11
Pin Name
SED1355
8-bit host bus interface
101 = MIPS/ISA bus interface
Little Endian
WAIT# is active high (1 = insert wait state)
Alternate Host Bus Interface Selected
= configuration for NEC VR4102/VR4111 microprocessor
R
4102/V
The SED1355 latches MD15 through MD0 to allow selection of the bus mode and other
configuration data on the rising edge of RESET#. For details on configuration, refer to the
SED1355 Hardware Functional Specification, document number X23A-A-001-xx.
The table below shows those configuration settings important to the NEC V
CPU interface.
NEC V
necessary to map an external LCD controller. Physical address 0A00 0000h to 0AFF
FFFFh (16M bytes) is reserved for an external LCD controller.
The SED1355 supports up to 2M bytes of display buffer. The NEC V
address line A21 is used to select between the SED1355 display buffer (A21=1) and
internal registers (A21=0).
The NEC V
address 0B00 0002h. It must be set to the value of 0001h to indicate that LCD controller
accesses using a non-inverting data bus.
R
4111 Configuration
value on this pin at rising edge of RESET# is used to configure:(1/0)
R
Table 4-1: Summary of Power-On/Reset Options
4102/V
R
4102/V
1
R
4111The NEC V
R
4111 has a 16-bit internal register named BCUCNTREG2 located at
R
4102/V
16-bit host bus interface
Big Endian
WAIT# is active low (0 = insert wait state)
Primary Host Bus Interface Selected
R
4111 provides the internal address decoding
0
R
4102/V
R
4102/V
X23A-G-007-05
R
4111
SED1355
R
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4111