sed1355 ETC-unknow, sed1355 Datasheet - Page 388

• Manufacturer Part Number: sed1355
• Description: Sed1355 Embedded Ramdac Lcd/crt Controller
• Manufacturer: ETC-unknow

Page 8
3.2 PR31500/PR31700 Host Bus Interface Signals
SED1355
X23A-G-001-06
When the SED1355 is configured to operate with the PR31500/PR31700, the host interface
requires the following signals:
• BUSCLK is a clock input required by the SED1355 host bus interface. It is separate
• Address input AB20 corresponds to the PR31500/PR31700 signal ALE (address latch
• Address input AB19 should be connected to the PR31500/PR31700 signal /CARDREG.
• Address input AB18 should be connected to the PR31500/PR31700 signal
• Address input AB17 should be connected to the PR31500/PR31700 signal
• Address inputs AB[16:13] and control inputs M/R#, CS# and BS# must be tied to V
• Address inputs AB[12:0], and the data bus DB[15:0], connect directly to the
• Control inputs WE1# and RD/WR# should be connected to the PR31500/PR31700
• Input RD# should be connected to the PR31500/PR31700 signal /RD. Either RD# or the
• Input WE0# should be connected to the PR31500/PR31700 signal /WR. Either WE0# or
• WAIT# is a signal output from the SED1355 that indicates the host CPU must wait until
from the input clock (CLKI) and should be driven by the PR31500/PR31700 bus clock
output DCLKOUT.
enable) whose falling edge indicates that the most significant bits of the address are
present on the multiplexed address bus (AB[12:0]).
This signal is active when either IO or configuration space of the PR31500/PR31700
PC Card slot is being accessed.
/CARDIORD. Either AB18 or the RD# input must be asserted for a read operation to
take place.
/CARDIOWR. Either AB17 or the WE0# input must be asserted for a write operation to
take place.
as they are not used in this interface mode.
PR31500/PR31700 address and data bus, respectively. MD4 must be set to select the
proper endian mode on reset (see Section 4.2, “SED1355 Configuration” on page 10).
Because of the PR31500/PR31700 data bus naming convention and endian mode,
SED1355 DB[15:8] must be connected to PR31500/PR31700 D[23:16], and
SED1355 DB[7:0] must be connected to PR31500/PR31700 D[31:24].
signals /CARDxCSH and /CARDxCSL respectively for byte steering.
AB18 input (/CARDIORD) must be asserted for a read operation to take place.
the AB17 input (/CARDIOWR) must be asserted for a write operation to take place.
data is ready (read cycle) or accepted (write cycle) on the host bus. Since the host CPU
accesses to the SED1355 may occur asynchronously to the display update, it is possible
that contention may occur in accessing the SED1355 internal registers and/or display
buffer. The WAIT# line resolves these contentions by forcing the host to wait until the
resource arbitration is complete.
Interfacing to the Philips MIPS PR31500/PR31700 Processor
Epson Research and Development
Vancouver Design Center
Issue Date: 99/05/05
DD