sed1355 ETC-unknow, sed1355 Datasheet - Page 110

• Manufacturer Part Number: sed1355
• Description: Sed1355 Embedded Ramdac Lcd/crt Controller
• Manufacturer: ETC-unknow

Page 104
bits 4-0
SED1355
X23A-A-001-11
bit 7
bit 6
bits 3-0
HRTC/FPLINE Start Position Register
REG[06h]
n/a
HRTC/FPLINE Pulse Width Register
REG[07h]
HRTC
Polarity
Select
n/a
FPLINE
Polarity
Select
FPLINE Polarity Select
Note
Note
HRTC/FPLINE Start Position Bits [4:0]
For CRT and TFT/D-TFD, these bits specify the delay from the start of the horizontal non-display
period to the leading edge of the HRTC pulse and FPLINE pulse respectively.
HRTC/FPLINE start position (pixels) = (HRTC/FPLINE Start Position Bits [4:0] + 1)
HRTC Polarity Select
This bit selects the polarity of the HRTC pulse to the CRT.
When this bit = 1, the HRTC pulse is active high.
When this bit = 0, the HRTC pulse is active low.
FPLINE Polarity Select
This bit selects the polarity of the FPLINE pulse to TFT/D-TFD or passive LCD.
When this bit = 1, the FPLINE pulse is active high for TFT/D-TFD and active low for passive LCD.
When this bit = 0, the FPLINE pulse is active low for TFT/D-TFD and active high for passive LCD.
HRTC/FPLINE Pulse Width Bits [3:0]
For CRT and TFT/D-TFD, these bits specify the pulse width of HRTC and FPLINE respectively.
For passive LCD, FPLINE is automatically created and these bits have no effect.
HRTC/FPLINE pulse width (pixels) = (HRTC/FPLINE Pulse Width Bits [3:0] + 1) 8
The maximum HRTC pulse width is 128 pixels.
This register must be programmed such that
(REG[05h] + 1)
This register must be programmed such that
(REG[05h] + 1)
0
1
n/a
n/a
Table 8-4: FPLINE Polarity Selection
Passive LCD FPLINE Polarity
(REG[06h] + 1) + (REG[07h] bits [3:0] +1)
n/a
(REG[06h] + 1) + (REG[07h] bits [3:0] +1)
HRTC/
FPLINE Start
Position Bit 4
active high
active low
HRTC/
FPLINE Start
Position Bit 3
HRTC/
FPLINE
Pulse Width
Bit 3
HRTC/
FPLINE Start
Position Bit 2
HRTC/
FPLINE
Pulse Width
Bit 2
TFT/D-TFD FPLINE Polarity
active high
active low
Epson Research and Development
HRTC/
FPLINE
Pulse Width
Bit 1
HRTC/
FPLINE Start
Position Bit 1
Hardware Functional Specification
Vancouver Design Center
Issue Date: 99/05/18
HRTC/
FPLINE Start
Position Bit 0
HRTC/
FPLINE
Pulse Width
Bit 0
8 - 2
RW
RW