sed1355 ETC-unknow, sed1355 Datasheet - Page 426

• Manufacturer Part Number: sed1355
• Description: Sed1355 Embedded Ramdac Lcd/crt Controller
• Manufacturer: ETC-unknow

Page 10
3 SED1355 Host Bus Interface
3.1 Host Bus Interface Pin Mapping
SED1355
X23A-G-007-05
Note
The SED1355 directly supports multiple processors. The SED1355 implements a 16-bit
MIPS/ISA Host Bus Interface which is most suitable for direct connection to the
VR4102/VR4111 microprocessor.
The MIPS/ISA host bus interface is selected by the SED1355 on the rising edge of
RESET#. After releasing reset the bus interface signals assume their selected configuration.
For details on SED1355 configuration, see Section 4.2, “SED1355 Hardware Configu-
ration” on page 13.
The following table shows the functions of each host bus interface signal.
At reset, the Host Interface Disable bit in the Miscellaneous Disable Register
(REG[1Bh] bit 7) is set to 1. This means that only REG[1Ah] (read-only) and
REG[1Bh] are accessible until a write to REG[1Bh] sets bit 7 to 0 making all regis-
ters accessible. When debugging a new hardware design, this can sometimes give the
appearance that the interface is not working, so it is important to remember to clear this
bit before proceeding with debugging.
SED1355 Pin Name
BUSCLK
RD/WR#
Table 3-1: Host Bus Interface Pin Mapping
AB[19:0]
DB[15:0]
RESET#
WAIT#
WE1#
WE0#
AB20
M/R#
CS#
RD#
BS#
NEC VR4102/VR4111 Pin Name
connected to system reset
Connected to V
Connected to V
ADD[19:0]
DAT[15:0]
LCDRDY
LCDCS#
BUSCLK
ADD20
ADD21
SHB#
WR#
RD#
Interfacing to the NEC VR4102/VR4111™ Microprocessors
DD
DD
Epson Research and Development
Vancouver Design Center
Issue Date: 99/05/05