sed1355 ETC-unknow, sed1355 Datasheet - Page 387
sed1355
Manufacturer Part Number
sed1355
Description
Sed1355 Embedded Ramdac Lcd/crt Controller
Manufacturer
ETC-unknow
Datasheet
1.SED1355.pdf
(509 pages)
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Epson Research and Development
Vancouver Design Center
3 SED1355 Host Bus Interface
3.1 PR31500/PR31700 Host Bus Interface Pin Mapping
Interfacing to the Philips MIPS PR31500/PR31700 Processor
Issue Date: 99/05/05
Note
The SED1355 implements a 16-bit host bus interface specifically for interfacing to the
PR31500/PR31700 microprocessor.
The PR31500/PR31700 host bus interface is selected by the SED1355 on the rising edge of
RESET#. After releasing reset, the bus interface signals assume their selected
configuration. For details on SED1355 configuration, see Section 4.2, “SED1355 Config-
uration” on page 10.
The following table shows the function of each host bus interface signal.
Table 3-1: PR31500/PR31700 Host Bus Interface Pin Mapping
At reset, the Host Interface Disable bit in the Miscellaneous Disable Register
(REG[1Bh] bit 7) is set to 1. This means that only REG[1Ah] (read-only) and
REG[1Bh] are accessible until a write to REG[1Bh] sets bit 7 to 0 making all regis-
ters accessible. When debugging a new hardware design, this can sometimes give the
appearance that the interface is not working, so it is important to remember to clear this
bit before proceeding with debugging.
SED1355 Pin Name
AB[16:13]
BUSCLK
DB[15:8]
RD/WR#
RESET#
AB[12:0]
DB[7:0]
WAIT#
WE1#
WE0#
AB20
AB19
AB18
AB17
M/R#
RD#
CS#
BS#
Philips PR31500/PR31700
/CARDxWAIT
/CARDIOWR
/CARDxCSH
/CARDIORD
/CARDxCSL
/CARDREG
DCLKOUT
D[23:16]
D[31:24]
RESET#
A[12:0]
ALE
V
V
V
V
/WE
/RD
DD
DD
DD
DD
X23A-G-001-06
SED1355
Page 7
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