sed1355 ETC-unknow, sed1355 Datasheet - Page 487

no-image

sed1355

Manufacturer Part Number
sed1355
Description
Sed1355 Embedded Ramdac Lcd/crt Controller
Manufacturer
ETC-unknow
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
sed1355F0A
Manufacturer:
EPSON/爱普生
Quantity:
20 000
Part Number:
sed1355FOA
Manufacturer:
EPSON
Quantity:
996
Part Number:
sed1355FOA
Manufacturer:
EPSON/爱普生
Quantity:
20 000
Epson Research and Development
Vancouver Design Center
4.2 SED1355 Configuration
4.3 NEC V
Interfacing to the NEC VR4121™ Microprocessor
Issue Date: 99/05/05
MD0
MD[3:1]
MD4
MD5
MD11
Pin Name
SED1355
8-bit host bus interface
101 = MIPS/ISA host bus interface
Little Endian
WAIT# is active high (1 = insert wait state)
Alternate Host Bus Interface Selected
= configuration for NEC VR4121 microprocessor
R
4121 Configuration
Note
The SED1355 latches MD15 through MD0 to allow selection of the bus mode and other
configuration data on the rising edge of RESET#. For details on configuration, refer to the
SED1355 Hardware Functional Specification, document number X23A-A-001-xx.
The table below shows those configuration settings relevant to the MIPS/ISA host bus
interface used by the NEC V
The NEC V
that the reserved address space is for the LCD controller, and not for the high-speed ISA
memory. The register BCUCNTREG2 bit GMODE must be set to 1 to indicate that a
non-inverting data bus is used for LCD controller accesses.
The LCD interface must be set to operate using a 16-bit data bus. This is accomplished by
setting the NEC V
The frequency of BUSCLK output is programmed from the state of pins TxD/CLKSEL2,
RTS#/CLKSEL1 and DTR#/CLKSEL0 during reset, and from the PMU (Power
Management Unit) configuration registers of the NEC V
of the frequencies provided by the NEC V
Setting the register BCUCNTREG3 bit LCD32/ISA32 to 0 affects both the LCD con-
troller and high-speed ISA memory access.
value on this pin at rising edge of RESET# is used to configure:(1/0)
Table 4-1: Summary of Power-On-Reset Options
R
4121 register BCUCNTREG1 bit ISAM/LCD must be set to 0. A 0 indicates
1
R
4121 register BCUCNTREG3 bit LCD32/ISA32 to 0.
R
4121 microprocessor.
16-bit host bus interface
Big Endian
WAIT# is active low (0 = insert wait state)
Primary Host Bus Interface Selected
R
4121.
R
4121. The SED1355 works at any
0
X23A-G-011-03
SED1355
Page 13

Related parts for sed1355