sed1355 ETC-unknow, sed1355 Datasheet - Page 50

• Manufacturer Part Number: sed1355
• Description: Sed1355 Embedded Ramdac Lcd/crt Controller
• Manufacturer: ETC-unknow

Page 44
SED1355
X23A-A-001-11
Symbol
t11
t10
t12
t13
t14
t15
t16
t9
t1
t2
t3
t4
t5
t6
t7
t8
2
1
Clock period
Clock pulse width high
Clock pulse width low
A[20:0], M/R#, RD/WR# setup to CKIO
A[20:0], M/R#, RD/WR# hold from CS#
BS# setup
BS# hold
CSn# setup
Falling edge RD# to D[15:0] driven
Rising edge CSn# to WAIT# tri-state
Falling edge CSn# to WAIT# driven
CKIO to WAIT# delay
D[15:0] setup to 2
D[15:0] hold (write cycle)
D[15:0] valid to WAIT# rising edge (read cycle)
Rising edge RD# to D[15:0] tri-state (read cycle)
1.
2.
If the SED1355 host interface is disabled, the timing for WAIT# driven is relative to the falling
edge of CSn# or the first positive edge of CKIO after A[20:0], M/R# becomes valid,
whichever one is later.
If the SED1355 host interface is disabled, the timing for D[15:0] driven is relative to the falling
edge of RD# or the first positive edge of CKIO after A[20:0], M/R# becomes valid,
whichever one is later.
nd
CKIO after BS# (write cycle)
a
b
Two Software WAIT States Required
One Software WAIT State Required
Parameter
Table 7-2: SH-3 Timing
15.1
Min
10
6
6
3
0
4
1
4
0
5
0
4
0
0
5
3.0V
a
Max
25
15
20
25
Epson Research and Development
Hardware Functional Specification
15.1
Min
2.5
3.6
2.5
10
6
6
3
0
4
1
4
0
0
0
0
Vancouver Design Center
5.0V
Issue Date: 99/05/18
b
Max
10
10
12
10
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns