sed1355 ETC-unknow, sed1355 Datasheet - Page 167

• Manufacturer Part Number: sed1355
• Description: Sed1355 Embedded Ramdac Lcd/crt Controller
• Manufacturer: ETC-unknow

Epson Research and Development
Vancouver Design Center
2.1 Miscellaneous
Display FIFO Threshold
Memory Address Offset
Half Frame Buffer Disable
Programming Notes and Examples
Issue Date: 99/04/27
This section of the notes contains recommendations which can be set at initialization time to improve
display image quality.
At high color depths the display FIFO introduces two conditions which must be accounted for in
software. Simultaneous display while using a dual passive panel introduces another possible register
change.
At 15/16 bit-per-pixel the display FIFO threshold (bits 0-4 of register [23h]) must be programmed
to a value other than ’0’. Product testing has shown that at these color depths a better quality image
results when the display FIFO threshold is set to a value of 1Bh.
When an 800x600 display mode is selected at 15 or 16 bpp, memory page breaks can disrupt the
display buffer fetches. This disruption produces a visible flicker on the display. To avoid this set the
Memory Address Offset (Reg [16h] and Reg [17h]) to 200h. This sets a 1024 pixel line which aligns
the memory page breaks and reduces any flicker.
The half frame buffer is an SED1355 mechanism which pre-digitizes display data for dual panel
displays. However, for proper simultaneous display operation the half frame buffer (HFB) must be
disabled. When running simultaneous display with a dual panel the pattern used by the Frame Rate
Modulator may need to be adjusted. This can be accomplished using the Alternate FRM Register
Reg[31h]. In this case, the recommended value for Reg[31h] of FFh, may produce more visually
appealing output. For further information on the half frame buffer and the Alternate FRM Register
see the SED1355 Hardware Functional Specification, document number X23A-A-001-xx.
X23A-G-003-05
SED1355
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