sed1355 ETC-unknow, sed1355 Datasheet - Page 446

• Manufacturer Part Number: sed1355
• Description: Sed1355 Embedded Ramdac Lcd/crt Controller
• Manufacturer: ETC-unknow

Page 14
3.2 PowerPC Host Bus Interface Signals
SED1355
X23A-G-008-03
The interface requires the following signals:
• BUSCLK is a clock input which is required by the SED1355 host bus interface. It is
• The address inputs AB[20:0], and the data bus DB[15:0], connect directly to the
• M/R# (memory/register) selects between memory or register access. It may be
• Chip Select (CS#) must be driven low whenever the SED1355 is accessed by the
• WE0# and WE1# connect to TSIZ1 and BI (the write enables for the low-order and
• RD# and RD/WR# connect to TSIZ0 and RD/WR (the read enables for the low-order
• WAIT# connects to TA and is a signal output from the SED1355 that indicates the
• The Bus Start (BS#) signal connects to TS (the transfer start signal).
separate from the input clock (CLKI) and is typically driven by the host CPU system
clock.
PowerPC bus address (A[11:31]) and data bus (D[0:15]), respectively. MD4 must be set
to select the proper endian mode upon reset.
connected to an address line, allowing system address A21 to be connected to the M/R#
line.
PowerPC bus.
high-order bytes). They must be driven low when the PowerPC bus is writing data to the
SED1355. These signals must be generated by external hardware based on the control
outputs from the PowerPC bus.
and high-order bytes). They must be driven low when the PowerPC bus is reading data
from the SED1355. These signals must be generated by external hardware based on the
control outputs from the PowerPC bus.
PowerPC bus must wait until data is ready (read cycle) or accepted (write cycle) on the
host bus. Since the PowerPC bus accesses to the SED1355 may occur asynchronously to
the display update, it is possible that contention may occur in accessing the SED1355
internal registers and/or display buffer. The WAIT# line resolves these contentions by
forcing the host to wait until the resource arbitration is complete.
Interfacing to the Motorola MPC821 Microprocessor
Epson Research and Development
Vancouver Design Center
Issue Date: 99/05/05