sed1355 ETC-unknow, sed1355 Datasheet - Page 164

• Manufacturer Part Number: sed1355
• Description: Sed1355 Embedded Ramdac Lcd/crt Controller
• Manufacturer: ETC-unknow

Page 8
2 Initialization
SED1355
X23A-G-003-05
Register
[1B]
[0A]
[23]
[01]
[22]
[02]
[03]
[04]
[05]
[06]
[07]
[08]
[09]
0000 0000 Enable the host interface
1000 0000 Disable the FIFO
0011 0000
0100 1000
0001 0110 Panel type - non-EL, 8-bit data, format 1, color, dual, passive
0000 0000 Mod rate used by older monochrome panels - set to 0
0100 1111 Horizontal display size = (Reg[04]+1)*8 = (79+1)*8 = 640 pixels
0000 0011
0000 0000 FPLINE start position - only required for CRT or TFT/D-TFD
0000 0000 FPLINE polarity set to active high
1110 1111 Vertical display size = Reg[09][08] + 1
0000 0000
0011 1000 Vertical non-display size = Reg[0A] + 1 = 57 + 1 = 58 lines
Value
Note
This section describes how to initialize the SED1355. Sample code to perform the initialization is
provided in the file INIT1355.C available from Epson.
SED1355 initialization can be broken into three steps. First, enable the SED1355 controller (if
necessary identify the specific controller). Next, set all the registers to their initial values. Finally,
program the Look-Up Table (LUT) with color values. This section does not deal with programming
the LUT, see Section 4 of this manual for LUT programming details.
The following table represents the sequence and values written to the SED1355 registers to control
a configuration with these specifications:
• 640x480 color dual passive format 1 LCD @ 75Hz.
• 8-bit data interface.
• 8 bit-per-pixel (bpp) - 256 colors.
• 31.5 MHz input clock.
• 50 ns EDO-DRAM, 2 CAS, 4 ms refresh, CAS before RAS.
When using an ISA evaluation board in a PC (i.e. SDU1355B0C), there are two additional steps
that must be carried out before initialization. First, confirm that 16-bit mode is enabled by writ-
ing to address F80000h. Then, if hardware suspend is enabled, disable suspend mode by writing
to F00000h. For further information on ISA evaluation boards refer to the SDU1355B0C Rev. 1.0
ISA Bus Evaluation Board User Manual, document number X23A-G-004-xx.
Memory configuration
- divide ClkI by 512 to get 4 ms for 256 refresh cycles
- this is 2-CAS# EDO memory
Performance Enhancement 0 - refer to the hardware
specification for a complete description of these bits
Horizontal non-display size = (Reg[05]+1)*8 = (3+1)*8 = 32
pixels
= 0000 0000 1110 1111 + 1
= 239+1 = 240 lines (total height/2 for dual panels)
Table 2-1: SED1355 Initialization Sequence
Notes
Epson Research and Development
Programming Notes and Examples
SED1355 Hardware
Functional Specification,
document number
X23A-A-001-xx
see note for REG[16h] and
REG[17h]
Vancouver Design Center
Issue Date: 99/04/27
See Also