sed1355 ETC-unknow, sed1355 Datasheet - Page 40

• Manufacturer Part Number: sed1355
• Description: Sed1355 Embedded Ramdac Lcd/crt Controller
• Manufacturer: ETC-unknow

AB[16:13] A[16:13] A[16:13] A[16:13]
SED1355
BUSCLK
AB[12:1]
DB[15:8]
RD/WR# RD/WR# RD/WR#
RESET# RESET# RESET# RESET#
Names
DB[7:0]
WAIT#
Page 34
WE1#
WE0#
5.4 Multiple Function Pin Mapping
AB20
AB19
AB18
AB17
M/R#
SED1355
X23A-A-001-11
RD#
AB0
CS#
BS#
Pin
A[12:1]
D[15:8]
WAIT#
D[7:0]
WE1#
WE0#
CKIO
SH-3
RD#
BS#
A20
A19
A18
A17
A0
1
A[12:1]
D[15:8]
D[7:0]
WE1#
WE0#
CKIO
SH-4
RDY
RD#
BS#
A20
A19
A18
A17
A0
Note
1
DTACK# DSACK1#
The bus signal A0 is not used by the SED1355 internally.
MC68K
D[15:8]
A[12:1]
Bus 1
D[7:0]
UDS#
LDS#
R/W#
CLK
AS#
V
V
A20
A19
A18
A17
External Decode
External Decode
DD
DD
D[31:24]
RESET#
A[16:13]
D[23:16]
MC68K
A[12:1]
Bus 2
R/W#
SIZ1
SIZ0
DS#
CLK
AS#
A20
A19
A18
A17
A0
Table 5-6: CPU Interface Pin Mapping
RESET#
Generic MIPS/ISA
A[16:13]
D[15:8]
A[12:1]
WAIT#
D[7:0]
WE1#
WE0#
BCLK
RD1#
RD0#
A20
A19
A18
A17
V
A0
DD
1
IOCHRDY /CARDxWAIT CARDxWAIT*
LatchA20
SA[16:13]
SD[15:8]
MEMW#
MEMR#
SA[12:1]
inverted
SD[7:0]
RESET
SBHE#
SA19
SA18
SA17
SA0
CLK
V
V
DD
DD
/CARDIOWR CARDIOWR*
/CARDxCSH
/CARDIORD
/CARDxCSL
/CARDREG
DCLKOUT
/PR31700
PR31500
D[31:24]
RESET#
D[23:16]
Philips
A[12:1]
ALE
/WE
V
V
A0
/RD
DD
DD
1
V
V
DD
DD
CARDxCSH*
CARDIORD*
CARDxCSL*
CARDREG*
DCLKOUT
Epson Research and Development
D[31:24]
D[23:16]
Toshiba
TX3912
A[12:1]
PON*
Hardware Functional Specification
WE*
ALE
V
V
RD*
A0
DD
DD
1
Vancouver Design Center
PowerPC
CLKOUT
RD/WR#
RESET#
A[15:18]
A[19:30]
Issue Date: 99/05/18
D[8:15
D[0:7]
TSIZ0
TSIZ1
External Decode
External Decode
A11
A12
A14
A31
TS#
TA#
A13
BI#
(PCMCIA)
PC Card
A[16:13]
inverted
D[15:8]
RESET
A[12:1]
-WAIT
D[7:0]
-CE2
CLKI
-CE1
-WE
A20
A19
V
-OE
A18
A17
A0
DD
1