sed1355 ETC-unknow, sed1355 Datasheet - Page 425

• Manufacturer Part Number: sed1355
• Description: Sed1355 Embedded Ramdac Lcd/crt Controller
• Manufacturer: ETC-unknow

Epson Research and Development
Vancouver Design Center
2.1.2 LCD Memory Access Cycles
Interfacing to the NEC VR4102/VR4111™ Microprocessors
Issue Date: 99/05/05
ADD[25:0]
WR#,RD#
LCDRDY
LCDCS#
D[15:0]
D[15:0]
(write)
(read)
SHB#
TCLK
Once an address in the LCD block of memory is placed on the external address bus
(ADD[25:0]), the LCD chip select (LCDCS#) is driven low. The read or write enable
signals (RD# or WR#) are driven low for the appropriate cycle and LCDRDY is driven low
to insert wait states into the cycle. The high byte enable (SHB#) in conjunction with address
bit 0 allows for byte steering.
The following figure illustrates typical NEC VR4102/VR4111 memory read and write
cycles to the LCD controller interface.
Figure 2-1: NEC VR4102/VR4111 Read/Write Cycles
Hi-Z
VALID
VALID
VALID
X23A-G-007-05
SED1355
Hi-Z
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