sed1355 ETC-unknow, sed1355 Datasheet - Page 241

• Manufacturer Part Number: sed1355
• Description: Sed1355 Embedded Ramdac Lcd/crt Controller
• Manufacturer: ETC-unknow

Epson Research and Development
Vancouver Design Center
Programming Notes and Examples
Issue Date: 99/04/27
*(pRegs + 0x0F) = 0x03;
/*
** Registers 10-12: Screen 1 Display Start Address - start at the
**
*/
*(pRegs + 0x10) = 0x00;
*(pRegs + 0x11) = 0x00;
*(pRegs + 0x12) = 0x00;
/*
** Register 13-15: Screen 2 Display Start Address - not applicable
**
*/
*(pRegs + 0x13) = 0x00;
*(pRegs + 0x14) = 0x00;
*(pRegs + 0x15) = 0x00;
/*
** Register 16-17: Memory Address Offset - this address represents the
**
**
*/
*(pRegs + 0x16) = 0x40;
*(pRegs + 0x17) = 0x01;
/*
** Register 18: Pixel Panning
*/
*(pRegs + 0x18) = 0x00;
/*
** Register 19: Clock Configuration - In this case we must divide
**
**
*/
*(pRegs + 0x19) = 0x01;
/*
** Register 1A: Power Save Configuration - enable LCD power, CBR refresh,
**
*/
*(pRegs + 0x1A) = 0x00;
/*
** Register 1C-1D: MD Configuration Readback - these registers are
**
**
*/
*(pRegs + 0x1C) = 0x00;
*(pRegs + 0x1D) = 0x00;
/*
** Register 1E-1F: General I/O Pins Configuration
*/
*(pRegs + 0x1E) = 0x00;
*(pRegs + 0x1F) = 0x00;
PCLK by 2 to arrive at the best frequency to set
our desired panel frame rate.
not suspended.
unless setting up for split screen operation.
starting WORD. At 8BPP our 640 pixel width is 320
WORDS
read only, but it’s OK to write a 0 to keep
the register configuration logic simpler.
first byte in display memory.
/* 0000 0011 */
/* 0000 0000 */
/* 0000 0000 */
/* 0000 0000 */
/* 0000 0000 */
/* 0000 0000 */
/* 0000 0000 */
/* 0100 0000 */
/* 0000 0001 */
/* 0000 0000 */
/* 0000 0001 */
/* 0000 0000 */
/* 0000 0000 */
/* 0000 0000 */
/* 0000 0000 */
/* 0000 0000 */
X23A-G-003-05
SED1355
Page 85