sed1355 ETC-unknow, sed1355 Datasheet - Page 120

• Manufacturer Part Number: sed1355
• Description: Sed1355 Embedded Ramdac Lcd/crt Controller
• Manufacturer: ETC-unknow

Page 114
SED1355
X23A-A-001-11
bit 3
bit 2
bit 1
General IO Pins Configuration Register 0
REG[1Eh]
n/a
General IO Pins Configuration Register 1
REG[1Fh]
n/a
n/a
n/a
rising edge of
MD[7:6] at
RESET#
Pins MA9, MA10, MA11 are multi-functional – they can be DRAM address outputs or general
purpose IO dependent on the DRAM type. MD[7:6] are used to identify the DRAM type and
configure these pins as follows:
These bits are used to control the direction of these pins when they are used as general purpose IO.
These bits have no effect when the pins are used as DRAM address outputs.
GPIO3 Pin IO Configuration
When this bit = 1, the GPIO3 pin is configured as an output pin.
When this bit = 0 (default), the GPIO3 pin is configured as an input pin.
GPIO2 Pin IO Configuration
When this bit = 1, the GPIO2 pin is configured as an output pin.
When this bit = 0 (default), the GPIO2 pin is configured as an input pin.
GPIO1 Pin IO Configuration
When this bit = 1, the GPIO1 pin is configured as an output pin.
When this bit = 0 (default), the GPIO1 pin is configured as an input pin.
This register position is reserved for future use.
00
01
10
11
n/a
n/a
Table 8-11: MA/GPIO Pin Functionality
GPIO3
n/a
n/a
MA9
MA9
MA9
MA9
GPIO3 Pin
IO Config.
n/a
Pin Function
GPIO1
GPIO1
GPIO1
MA10
MA10
GPIO2 Pin
IO Config.
n/a
GPIO2
GPIO2
GPIO2
MA11
MA11
Epson Research and Development
n/a
GPIO1 Pin
IO Config.
Hardware Functional Specification
Vancouver Design Center
Issue Date: 99/05/18
n/a
n/a
RW
RW