sed1355 ETC-unknow, sed1355 Datasheet - Page 71

• Manufacturer Part Number: sed1355
• Description: Sed1355 Embedded Ramdac Lcd/crt Controller
• Manufacturer: ETC-unknow

Epson Research and Development
Vancouver Design Center
Hardware Functional Specification
Issue Date: 99/05/18
Symbol
t10
t11
t1
t2
t3
t4
t5
t6
t7
t8
t9
MD(Read)
MD(Write)
Memory
RAS#
CAS#
Clock
WE#
MA
Internal memory clock period
Random read cycle REG[22h] bit 6-5 == 00
Random read cycle REG[22h] bit 6-5 == 01
Random read cycle REG[22h] bit 6-5 == 10
RAS# precharge time (REG[22h] bits 3-2 = 00)
RAS# precharge time (REG[22h] bits 3-2 = 01)
RAS# precharge time (REG[22h] bits 3-2 = 10)
RAS# to CAS# delay time (REG[22h] bit 4 = 0 and
bits 3-2 = 00 or 10)
RAS# to CAS# delay time (REG[22h] bit 4 = 1 and
bits 3-2 = 00 or 10)
RAS# to CAS# delay time (REG[22h] bits 3-2 = 01)
CAS# precharge time
CAS# pulse width
RAS# hold time
Row address setup time (REG[22h] bits 3-2 = 00)
Row address setup time (REG[22h] bits 3-2 = 01)
Row address setup time (REG[22h] bits 3-2 = 10)
Row address hold time (REG[22h] bits 3-2 = 00 or
10)
Row address hold time (REG[22h] bits 3-2 = 01)
Column address setup time
Column address hold time
t8
t3
t1
R
t12
Parameter
t9
Table 7-15: EDO-DRAM Read/Write/Read-Write Timing
t4
t10 t11
Figure 7-15: EDO-DRAM Read-Write Timing
C1
t5
t14
t6
d1
C2
t15
t1
d2
C3
t23
t25
0.45 t1 - 3
1.45 t1 - 3
0.45 t1 - 3
0.45 t1 - 3
0.45 t1 - 3
0.45 t1 - 3
1.45 t1 - 3
d3
1 t1 - 3
1 t1 - 3
2.45 t1
1.45 t1
2t1 - 3
1t1 - 3
2t1 - 3
1t1 - 3
Min
2 t1
5t1
4t1
3t1
25
t26
C1
t24
t20 t21
d1
C2
d2
Max
C3
d3
t19
t22
t7
X23A-A-001-11
SED1355
Units
Page 65
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