mcf5407 Freescale Semiconductor, Inc, mcf5407 Datasheet - Page 89

• Manufacturer Part Number: mcf5407
• Description: Mcf5407 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

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CPUSHL
HALT
INTOUCH
MOVE from SR
MOVE to SR
MOVEC
RTE
STOP
WDEBUG
2.7 Execution Timings
The timing data presented in this section assumes the following:
The HALT instruction can be configured to allow user-mode execution by setting CSR[UHE].
Instruction
• Execution times are shown for individual instructions without assumptions
• The OEP is loaded with the opword and all required extension words at the
• The OEP experiences no sequence-related pipeline stalls. For the MCF5407, the
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regarding the OEP’s ability to dispatch multiple instructions at a time. For sequences
where instruction pairs are issued, the execution time of the two instructions is
defined by the execution time of the first instruction; that is, the second instruction
effectively executes in zero cycles.
beginning of each instruction execution. This implies that the OEP spends no time
waiting for the IFP to supply opwords and/or extension words.
most common example of such a stall occurs when a register is modified in the EX
compute engine and a subsequent instruction generating an address uses the
previously modified register. The second instruction stalls in the OEP until the
register is updated by the previous instruction. For example:
muls.l
move.l
(An)
none
(Ay)
SR, Dx
Dy,SR
#<data>,SR
Ry,Rc
None
#<data>
<ea-2>y
Operand Syntax Operand Size
Table 2-9. Supervisor-Level Instruction Set Summary
#<data>,d0
(a0,d0.l*4),d1
Unsized
Unsized
Unsized
.W
.W
.L
Unsized
.W
.L
Chapter 2. ColdFire Core
Invalidate instruction cache line
Push and invalidate data cache line
Push data cache line and invalidate (I,D)-cache lines
Enter halted state
Touch instruction space at address Ay
SR → Dx
Source → SR
Ry → Rc
Rc
0x002
0x004
0x005
0x006
0x007
0x801
0xC04 RAM base address register 0 (RAMBAR0)
0xC05 RAM base address register 1 (RAMBAR1)
(SP+2) → SR; SP+4 → SP; (SP) → PC; SP + formatfield  SP
Immediate data → SR; enter stopped state
<ea-2>y → debug module
Register Definition
Cache control register (CACR)
Access control register 0 (ACR0)
Access control register 1 (ACR1)
Access control register 2 (ACR2)
Access control register 3 (ACR3)
Vector base register (VBR)
Operation
Execution Timings
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