mcf5407 Freescale Semiconductor, Inc, mcf5407 Datasheet - Page 8

• Manufacturer Part Number: mcf5407
• Description: Mcf5407 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

Paragraph
Number
4.9.2
4.9.3
4.9.3.1
4.9.3.2
4.9.3.3
4.9.3.4
4.9.4
4.9.5
4.9.5.1
4.9.5.2
4.9.5.2.1
4.9.5.2.2
4.9.6
4.10
4.10.1
4.10.2
4.11
4.12
4.12.1
4.12.2
4.13
5.1
5.2
5.2.1
5.3
5.3.1
5.3.2
5.3.3
5.4
5.4.1
5.4.2
5.4.3
5.4.4
5.4.5
5.4.6
5.4.7
5.4.8
viii
Cache Registers................................................................................................. 4-21
Cache Management........................................................................................... 4-24
Cache Operation Summary ............................................................................... 4-27
Cache Initialization Code.................................................................................. 4-32
Overview............................................................................................................. 5-1
Signal Descriptions ............................................................................................. 5-2
Real-Time Trace Support.................................................................................... 5-4
Programming Model ........................................................................................... 5-8
Cache-Inhibited Accesses ............................................................................. 4-14
Cache Protocol.............................................................................................. 4-15
Cache Coherency (Data Cache Only)........................................................... 4-17
Memory Accesses for Cache Maintenance................................................... 4-17
Cache Locking .............................................................................................. 4-19
Cache Control Register (CACR) .................................................................. 4-21
Access Control Registers (ACR0–ACR3).................................................... 4-23
Instruction Cache State Transitions .............................................................. 4-27
Data Cache State Transitions........................................................................ 4-28
Processor Status/Debug Data (PSTDDATA[7:0]) ......................................... 5-3
Begin Execution of Taken Branch (PST = 0x5) ............................................. 5-6
Processor Stopped or Breakpoint State Change (PST = 0xE) ........................ 5-7
Processor Halted (PST = 0xF) ........................................................................ 5-7
Address Attribute Trigger Registers (AATR, AATR1)................................ 5-10
Address Breakpoint Registers (ABLR/ABLR1, ABHR/ABHR1) ............. 5-12
BDM Address Attribute Register (BAAR)................................................... 5-12
Configuration/Status Register (CSR)............................................................ 5-13
Data Breakpoint/Mask Registers (DBR/DBR1, DBMR/DBMR1) ............ 5-15
Program Counter Breakpoint/Mask Registers
Trigger Definition Register (TDR) ............................................................... 5-18
Extended Trigger Definition Register (XTDR) ............................................ 5-19
Read Miss ................................................................................................. 4-16
Write Miss (Data Cache Only) ................................................................. 4-16
Read Hit .................................................................................................... 4-16
Write Hit (Data Cache Only) .................................................................... 4-17
Cache Filling............................................................................................. 4-17
Cache Pushes ............................................................................................ 4-18
(PBR, PBR1, PBR2, PBR3, PBMR) ........................................................ 5-16
Push and Store Buffers ......................................................................... 4-18
Push and Store Buffer Bus Operation................................................... 4-18
MCF5407 User’s Manual
CONTENTS
Debug Support
Chapter 5
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Number
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