mcf5407 Freescale Semiconductor, Inc, mcf5407 Datasheet - Page 86

• Manufacturer Part Number: mcf5407
• Description: Mcf5407 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

ADDI
ADDQ
ADDX
AND
ANDI
ASL
ASR
Bcc
BCHG
BCLR
BRA
BSET
BSR
BTST
CLR
CMP
CMPA
CMPI
DIVS
DIVU
EOR
EORI
EXT
EXTB
HALT
JMP
JSR
LEA
Instruction
Instruction Set Summary
2-20
1
#<data>,Dx
#<data>,<ea>x
Dy,Dx
Dy,<ea>x
<ea>y,Dx
#<data>,Dx
Dy,Dx
#<data>,Dx
Dy,Dx
#<data>,Dx
<label>
Dy,<ea>x
#<data>,<ea-1>x
Dy,<ea>x
#<data>,<ea-1>x
<label>
Dy,<ea>x
#<data>,<ea-1>x
<label>
Dy,<ea>x
#<data>,<ea-1>x
<ea>y,Dx
<ea>y,Ax
<ea>y,Dx
<ea>y,Dx
<ea-1>y,Dx
<ea>y,Dx
<ea-1>y,Dx
Dy,<ea>x
Dy,<ea>x
#<data>,Dx
#<data>,Dx
Dx
None
<ea-3>y
<ea-3>y
<ea-3>y,Ax
Operand Syntax
Table 2-8. User-Level Instruction Set Summary (Continued)
.L
.L
.L
.L
.L
.L
.L
.L
.L
.L
.B,.W,.L
.B,.L
.B,.L
.B,.L
.B,.L
.B,.W,.L
.B,.L
.B,.L
.B,.W,.L
.B,.L
.B,.L
.B,.W,.L
.B,.W,.L
.W,.L
.B,.W,.L
.W
.L
.W
.L
.L
.L
.B →.W
.W →.L
.B →.L
Unsized
Unsized
Unsized
.L
Operand Size
MCF5407 User’s Manual
Immediate data + destination → destination
Immediate data + destination → destination
Source + destination + X → destination
Source & destination → destination
Immediate data & destination → destination
X/C ← (Dx << Dy) ← 0
X/C ← (Dx << #<data>) ← 0
MSB → (Dx >> Dy) → X/C
MSB → (Dx >> #<data>) → X/C
If condition true, then PC + 2 + d
~(<bit number> of destination) → Z,
Bit of destination
~(<bit number> of destination) → Z;
0 → bit of destination
PC + 2 + d
~(<bit number> of destination) → Z;
1→ bit of destination
SP – 4 → SP; next sequential PC→ (SP); PC + 2 + d
~(<bit number> of destination) → Z
0 → destination
Destination – source
Destination – source
Destination – immediate data
Dx /<ea>y → Dx {16-bit remainder; 16-bit quotient}
Dx /<ea>y → Dx {32-bit quotient}
Signed operation
Dx /<ea>y → Dx {16-bit remainder; 16-bit quotient}
Dx /<ea>y → Dx {32-bit quotient}
Unsigned operation
Source ^ destination → destination
Immediate data ^ destination → destination
Sign-extended destination → destination
Sign-extended destination → destination
Enter halted state
Address of <ea> → PC
SP – 4 → SP; next sequential PC → (SP); <ea> → PC
<ea> → Ax
n
→ PC
Operation
n
→ PC
n
→ PC