mcf5407 Freescale Semiconductor, Inc, mcf5407 Datasheet - Page 204

• Manufacturer Part Number: mcf5407
• Description: Mcf5407 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

Real-Time Debug Support
development system can use BDM commands to read the reserved memory locations.
The generation of another debug interrupt during the first instruction after the RTE exits
emulator mode is inhibited. This behavior is consistent with the existing logic involving
trace mode where the first instruction executes before another trace exception is generated.
Thus, all hardware breakpoints are disabled until the first instruction after the RTE
completes execution, regardless of the programmed trigger response.
5.6.1.1 Emulator Mode
Emulator mode is used to facilitate non-intrusive emulator functionality. This mode can be
entered in three different ways:
While operating in emulation mode, the processor exhibits the following properties:
The return-from-exception (RTE) instruction exits emulation mode. The processor status
output port provides a unique encoding for emulator mode entry (0xD) and exit (0x7).
5.6.2 Concurrent BDM and Processor Operation
The debug module supports concurrent operation of both the processor and most BDM
commands. BDM commands may be executed while the processor is running, except those
following operations that access processor/memory registers:
For BDM commands that access memory, the debug module requests the processor’s local
bus. The processor responds by stalling the instruction fetch pipeline and waiting for
current bus activity to complete before freeing the local bus for the debug module to
perform its access. After the debug module bus cycle, the processor reclaims the bus.
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• Setting CSR[EMU] forces the processor into emulator mode. EMU is examined
• A debug interrupt always puts the processor in emulation mode when debug
• Setting CSR[TRC] forces the processor into emulation mode when trace exception
• Unmasked interrupt requests are serviced. The resulting interrupt exception stack
• If CSR[MAP] = 1, all caching of memory and the SRAM module are disabled. All
• Read/write address and data registers
• Read/write control registers
only if RSTI is negated and the processor begins reset exception processing. It can
be set while the processor is halted before reset exception processing begins. See
Section 5.5.1, “CPU Halt.”
interrupt exception processing begins.
processing begins.
frame has FS[1] set to indicate the interrupt occurred while in emulator mode.
memory accesses are forced into a specially mapped address space signaled by
TT = 2, TM = 5 or 6. This includes stack frame writes and the vector fetch for the
exception that forced entry into this mode.
MCF5407 User’s Manual