mcf5407 Freescale Semiconductor, Inc, mcf5407 Datasheet - Page 139

• Manufacturer Part Number: mcf5407
• Description: Mcf5407 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

In determining whether a memory location is cacheable or cache-inhibited, the CPU checks
memory-control registers in the following order:
Cache-inhibited write accesses bypass the cache and a corresponding external write is
performed. Cache-inhibited reads bypass the cache and are performed on the external bus,
except when all of the following conditions are true:
In this case, a fetched line is stored in the fill buffer and remains valid there; the cache can
service additional read accesses from this buffer until another fill occurs or a
cache-invalidate-all operation occurs.
If ACRn[CM] indicates cache-inhibited mode, precise or imprecise, the controller bypasses
the cache and performs an external transfer. If a line in the cache matches the address and
the mode is cache-inhibited, the cache does not automatically push the line if it is modified,
nor does it invalidate the line if it is valid. Before switching cache mode, execute a
CPUSHL instruction or set CACR[DCINVA,ICINVA] to invalidate the entire cache.
If ACRn[CM] indicates precise mode, the sequence of read and write accesses to the region
is guaranteed to match the instruction sequence. In imprecise mode, the processor core
allows read accesses that hit in the cache to occur before completion of a pending write
from a previous instruction. Writes are not deferred past data-read accesses that miss the
cache (that is, that must be read from the bus).
Precise operation forces data-read accesses for an instruction to occur only once by
preventing the instruction from being interrupted after data is fetched. Otherwise, if the
processor is not in precise mode, an exception aborts the instruction and the data may be
accessed again when the instruction is restarted. These guarantees apply only when
ACRn[CM] indicates precise mode and aligned accesses.
CPU space-register accesses, such as MOVEC, are treated as cache-inhibited and precise.
4.9.3 Cache Protocol
The following sections describe the cache protocol for processor accesses and assumes that
the data is cacheable (that is, write-through or copyback). Note that the discussion of write
operations applies to the data cache only.
1. RAMBARs
2. ACR0 and ACR2
3. ACR1 and ACR3
4. If an access does not hit in the RAMBARs or the ACRs, the default is provided for
• The cache-inhibited fill-buffer bit, CACR[DNFB], is set.
• The access is an instruction read.
• The access is normal (that is, TT = 0).
all accesses in CACR.
Chapter 4. Local Memory
Cache Operation
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