mcf5407 Freescale Semiconductor, Inc, mcf5407 Datasheet - Page 242
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mcf5407
Manufacturer Part Number
mcf5407
Description
Mcf5407 Coldfire Integrated Microprocessor User
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MCF5407.pdf
(546 pages)
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Programming Model
the resulting SCL bus signal low period is stretched.
8.5 Programming Model
Table 8-1 lists the configuration registers used in the I
8.5.1 I
The IADR holds the address the I
not the address sent on the bus during the address transfer.
Table 8-2 describes IADR fields.
8.5.2 I
The IFDR, Figure 8-6, provides a programmable prescaler to configure the clock for
8-6
7–1
0
Offset
0x28C
MBAR
Bits
0x280
0x284
0x288
0x290
ADR
—
Name
I
I
I
I
I
2
2
2
2
2
Address
2
2
C address register (IADR) [p. 8-6]
C frequency divider register (IFDR) [p. 8-6]
C control register (I2CR) [p. 8-7]
C status register (I2SR) [p. 8-8]
C data I/O register (I2DR) [p. 8-9]
C Address Register (IADR)
C Frequency Divider Register (IFDR)
Reset
Field
R/W
External masters cannot access the MCF5407’s on-chip
memories or MBAR, but can access any I
Slave address. Contains the specific slave address to be used by the I
the default I
Reserved, should be cleared.
Table 8-2. I
7
[31:24]
Figure 8-5. I
2
Table 8-1. I
C mode for an address match on the bus.
6
2
C Address Register Field Descriptions
2
MCF5407 User’s Manual
C responds to when addressed as a slave. Note that it is
2
2
5
C Address Register (IADR)
C Interface Memory Map
NOTE:
ADR
MBAR + 0x280
0000_0000
Read/Write
4
Description
[23:16]
2
3
C interface.
2
C module register.
2
Reserved
Reserved
Reserved
Reserved
Reserved
[15:8]
2
1
C module. Slave mode is
—
0
[7:0]
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