mcf5407 Freescale Semiconductor, Inc, mcf5407 Datasheet - Page 77

• Manufacturer Part Number: mcf5407
• Description: Mcf5407 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

2.2.2.1 Status Register (SR)
The SR stores the processor status, the interrupt priority mask, and other control bits.
Supervisor software can read or write the entire SR; user software can read or write only
SR[7–0], described in Section 2.2.1.5, “Condition Code Register (CCR).” The control bits
indicate processor states—trace mode (T), supervisor or user mode (S), and master or
interrupt state (M). SR is set to 0x27xx after reset.
Table 2-3 describes SR fields.
Reset
15
13
12
10–8
7–0
Field
Bits
R/W R/W
T
S
M
I
CCR
Name
15
T
0
—
14
R
0
Trace enable. When T is set, the processor performs a trace exception after every instruction.
Supervisor/user state. Indicates whether the processor is in supervisor or user mode
0 User mode
1 Supervisor mode
Master/interrupt state. Cleared by an interrupt exception. It can be set by software during execution
of the RTE or move to SR instructions so the OS can emulate an interrupt stack pointer.
Interrupt priority mask. Defines the current interrupt priority. Interrupt requests are inhibited for all
priority levels less than or equal to the current priority, except the edge-sensitive level-7 request,
which cannot be masked.
Condition code register. See Table 2-1.
R/W
13
S
1
Rc[11–0]
0xC04
0xC05
0xC0F
0x002
0x004
0x005
0x006
0x007
0x801
System byte
R/W
12
M
0
Table 2-3. Status Field Descriptions
Table 2-2. MOVEC Register Map
Figure 2-5. Status Register (SR)
11
—
Cache control register (CACR)
Access control register 0 (ACR0)
Access control register 1 (ACR1)
Access control register 2 (ACR2)
Access control register 3 (ACR3)
Vector base register (VBR)
RAM base address register 0 (RAMBAR0)
RAM base address register 1 (RAMBAR1)
Module base address register (MBAR)
R
0
Chapter 2. ColdFire Core
10
R/W
111
9
I
Register Definition
8
Description
7
000
—
R
6
Condition code register (CCR)
5
R/W
—
X
4
R/W
—
N
3
Programming Model
R/W
—
Z
2
R/W
—
V
1
2-11
R/W
—
C
0