mcf5407 Freescale Semiconductor, Inc, mcf5407 Datasheet - Page 17

• Manufacturer Part Number: mcf5407
• Description: Mcf5407 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

17.8.2
17.9
17.9.1
17.9.2
17.9.3
17.9.4
17.10
17.10.1
17.10.2
17.11
17.12
17.12.1
17.12.2
17.13
17.13.1
17.13.2
17.13.3
17.13.4
17.14
17.14.1
17.14.2
17.14.3
17.14.4
17.14.5
18.1
18.2
18.3
18.4
18.4.1
18.4.2
18.4.3
18.4.4
18.4.5
18.4.6
18.4.7
18.4.7.1
18.4.7.2
18.4.7.3
Paragraph
Number
Serial Module Signals ..................................................................................... 17-18
Timer Module Signals..................................................................................... 17-19
Parallel I/O Port (PP[15:0]) ............................................................................ 17-19
I
Debug and Test Signals .................................................................................. 17-20
Debug Module/JTAG Signals......................................................................... 17-21
Features ............................................................................................................. 18-1
Bus and Control Signals.................................................................................... 18-1
Bus Characteristics............................................................................................ 18-2
Data Transfer Operation ................................................................................... 18-2
2
C Module Signals......................................................................................... 17-20
Transfer Modifier/DMA Acknowledge (TM[2:0]/DACK[1:0]) ................ 17-18
Transmitter Serial Data Output (TxD)........................................................ 17-18
Receiver Serial Data Input (RxD)............................................................... 17-19
Clear to Send (CTS).................................................................................... 17-19
Request to Send (RTS) ............................................................................... 17-19
Timer Inputs (TIN[1:0]).............................................................................. 17-19
Timer Outputs (TOUT1, TOUT0) .............................................................. 17-19
I
I
Test Mode (MTMOD[3:0]) ........................................................................ 17-20
High Impedance (HIZ)................................................................................ 17-20
Processor Clock Output (PSTCLK)............................................................ 17-20
Processor Status Debug Data (PSTDDATA[7:0])...................................... 17-21
Test Reset/Development Serial Clock (TRST/DSCLK) ............................ 17-21
Test Mode Select/Breakpoint (TMS/BKPT) .............................................. 17-21
Test Data Input/Development Serial Input (TDI/DSI) ............................... 17-22
Test Data Output/Development Serial Output (TDO/DSO)....................... 17-22
Test Clock (TCK) ....................................................................................... 17-22
Bus Cycle Execution..................................................................................... 18-4
Data Transfer Cycle States ........................................................................... 18-5
Read Cycle.................................................................................................... 18-7
Write Cycle ................................................................................................... 18-8
Fast-Termination Cycles............................................................................... 18-9
Back-to-Back Bus Cycles ........................................................................... 18-10
Burst Cycles................................................................................................ 18-11
2
2
C Serial Clock (SCL) ............................................................................... 17-20
C Serial Data (SDA) ................................................................................ 17-20
Line Transfers ......................................................................................... 18-12
Line Read Bus Cycles............................................................................. 18-12
Line Write Bus Cycles............................................................................ 18-14
CONTENTS
Bus Operation
Chapter 18
Contents
Title
Number
Page
xvii