mcf5407 Freescale Semiconductor, Inc, mcf5407 Datasheet - Page 322

• Manufacturer Part Number: mcf5407
• Description: Mcf5407 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

DMA Controller Module Programming Model
12.4.5 DMA Status Registers (DSR0–DSR3)
In response to an event, the DMA controller writes to the appropriate DSRn bit,
Figure 12-9. Only a write to DSRn[DONE] results in action.
Table 12-5 describes DSRn fields.
15
14–0
12-10
Bits
7
6
5
4
3
2
Bits
—
CE
BES
BED
—
REQ
AT
—
Name
Name
Reserved, should be cleared.
Configuration error. Occurs when BCR, SAR, or DAR does not match the requested transfer size,
or if BCR = 0 when the DMA receives a start condition. CE is cleared at hardware reset or by
writing a 1 to DSR[DONE].
0 No configuration error exists.
1 A configuration error has occurred.
Bus error on source
0 No bus error occurred.
1 The DMA channel terminated with a bus error either during the read portion of a transfer or
Bus error on destination
0 No bus error occurred.
1 The DMA channel terminated with a bus error during the write portion of a transfer.
Reserved, should be cleared.
Request
0 No request is pending or the channel is currently active. Cleared when the channel is selected.
1 The DMA channel has a transfer remaining and the channel is not selected.
DMA acknowledge type. Controls whether acknowledge information is provided for the entire
transfer or only the final transfer.
0 Entire transfer. DMA acknowledge information is displayed anytime the channel is selected as the
1 Final transfer (when BCR reaches zero). For dual-address transfer, the acknowledge information
Reserved, should be cleared.
Address
during an access in single-address mode (SAA = 1).
result of an external request.
is displayed for both the read and write cycles.
Reset
Field
R/W
Table 12-4. DCRn Field Descriptions (Continued)
Figure 12-9. DMA Status Registers (DSRn)
—
—
7
Table 12-5. DSRn Field Descriptions
CE
0
6
MCF5407 User’s Manual
MBAR + 0x310, 0x350, 0x390, 0x3D0
BES
0
5
BED
0
4
Description
Description
R/W
—
—
3
REQ
0
2
BSY
0
1
DONE
0
0