mcf5407 Freescale Semiconductor, Inc, mcf5407 Datasheet - Page 146

• Manufacturer Part Number: mcf5407
• Description: Mcf5407 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

Cache Registers
4-22
27
26–25
24
23–20
19
18
17–16
15
14
13
12
Bits
DCINVA Data cache invalidate all. Writing a 1 to this bit initiates entire cache invalidation. Once
BCINVA Branch cache invalidate. Invalidation occurs when this bit is written as a 1. Note that branch
DHLCK
DDCM
Name
DNFB
BEC
IDPI
IEC
—
—
—
Half-data cache lock mode
0 Normal operation. The cache allocates the lowest invalid way. If all ways are valid, the cache
1 Half-cache operation. The cache allocates to the lower invalid way of levels 2 and 3; if both are
This implementation allows maximum use of available cache memory and provides the flexibility
of setting DHLCK before, during, or after allocations occur.
Default data cache mode. For normal operations that do not hit in the RAMBARs or ACRs, this
field defines the effective cache mode.
00 Cacheable write-through imprecise
01 Cacheable copyback
10 Cache-inhibited precise
11 Cache-inhibited imprecise
Precise and imprecise accesses are described in Section 4.9.2, “Cache-Inhibited Accesses.”
invalidation is complete, this bit automatically returns to 0; it is not necessary to clear it explicitly.
Note the caches are not cleared on power-up or normal reset, as shown in Figure 4-4.
0 No invalidation is performed.
1 Initiate invalidation of the entire data cache. The cache controller sequentially clears V and M
Reserved, should be cleared.
Enable branch cache. The branch cache is described in Section 2.1.2.1.1, “Branch Acceleration.”
0 Branch cache disabled. This may be useful if code is unlikely to be reused.
1 Branch cache enabled.
caches are not cleared on power-up or normal reset.
0 No invalidation is performed.
1 Initiate an invalidation of the entire branch cache.
Reserved. These bits must be cleared; otherwise performance may be affected.
Enable instruction cache
0 Instruction cache disabled. All instructions and tags in the cache are preserved.
1 Instruction cache enabled.
Reserved, should be cleared.
Default cache-inhibited fill buffer
0 Fill buffer does not store cache-inhibited instruction accesses (16 or 32 bits).
1 Fill buffer can store cache-inhibited accesses. The buffer is used only for normal (TT = 0)
Setting DNFB can cause a coherency problem for self-modifying code. If a cache-inhibited
access uses the buffer while DNFB = 1, instructions remain valid in the buffer until a
cache-invalidate-all instruction, another cache-inhibited burst, or a miss that initiates a fill. A write
to the line in the fill goes to the external bus without updating or invalidating the buffer.
Subsequent reads of that written data are serviced by the fill buffer and receive stale information.
Instruction CPUSHL invalidate disable.
0 Normal operation. A CPUSHL instruction causes the selected line to be invalidated.
1 No clear operation. A CPUSHL instruction causes the selected line to be left valid.
allocates the way pointed at by the counter and then increments this counter modulo-4.
valid, the cache allocates to way 2 if the high-order bit of the round-robin counter is zero;
otherwise, it allocates way 3 and increments the round-robin counter modulo-2. This locks the
content of ways 0 and 1. Ways 0 and 1 are still updated on write hits and may be pushed or
cleared by specific cache push/invalidate instructions.
bits in all sets. Subsequent data accesses stall until the invalidation is finished, at which point,
this bit is automatically cleared. In copyback mode, the cache should be flushed using a
CPUSHL instruction before setting this bit.
instruction reads of a cache-inhibited region. Instructions are loaded into the buffer by a burst
access (line fill). They stay in the buffer until they are displaced; subsequent accesses may not
appear on the external bus.
Table 4-4. CACR Field Descriptions (Continued)
MCF5407 User’s Manual
Description